Abstract: Disclosed herein is a semiconductor device that includes: a memory cell array including sub-word lines, bit lines and memory cells arranged at intersections of the sub-word lines and the bit lines; a plurality of sub-word drivers each drives an associated one of the sub-word lines; and a plurality of main word drivers each supplies a main word signal having one of a selected-level potential and an unselected-level potential to an associated one of the sub-word drivers. Each of the sub-word drivers drives the associated one of the sub-word lines to an active level when an associated one of the main word signals has the selected-level potential, and drives the associated one of the sub-word lines to an inactive level when the associated one of the main word signals has the unselected-level potential. The unselected-level potential of the main word signals is variable depending on an operation mode.

Abstract: A semiconductor device includes internal voltage generating circuits, a switching circuit, load circuits, a control circuit. Each of the plurality of load circuits is supplied with voltage through the switching circuit from any one of the plurality of internal voltage generating circuits. The control circuit defines connecting combinations by the switch circuit. The control circuit supplies a control signal to the switch circuit, based on the control signal corresponding to the definitions of the connecting combinations. The control circuit allows switching the connecting combinations when the semiconductor device tests in a test mode. The control circuit prohibits switching the connecting combinations in a non-test mode. The switch circuit connects between each of m of the internal voltage generating circuits and each of n of the load circuits through a connecting combination which is selected, based on the control signal, from mn of the connecting combinations.

Abstract: A semiconductor memory device simultaneously selects an object cell and a counter cell which connect with a common bit line, simultaneously activates sub-word lines of the object cell and the counter cell after predetermined levels are written in the object cell and the counter cell, simultaneously read data of the object cell and the counter cell from the common bit line, and hence, determines whether the object cell is normal or defective, based on a voltage level of the common bit line. Thereby, the defective cell in the semiconductor memory device can be reliably detected.

Abstract: A semiconductor memory device executes a refresh operation on memory banks, and includes: a command decoder that decodes a command from outside the semiconductor memory device, and outputs a refresh instruction when the command is an auto-refresh command; a refresh command generating unit that outputs a refresh command signal by a predetermined number of times corresponding to the number of word lines to be refreshed in response to the refresh instruction; a bank address counter that holds a bank address for selecting a memory bank to be refreshed, counts up the bank address every time the refresh command signal is output, and performs a carry-over action when count-up operations equivalent to the number of the memory banks are performed; and a row address counter that holds a row address for selecting a word line to be refreshed, and counts up the row address in response to the carry-over action.

Abstract: A semiconductor device includes internal voltage generating circuits, a switching circuit, load circuits, a control circuit. Each of the plurality of load circuits is supplied with voltage through the switching circuit from any one of the plurality of internal voltage generating circuits. The control circuit defines connecting combinations by the switch circuit. The control circuit supplies a control signal to the switch circuit, based on the control signal corresponding to the definitions of the connecting combinations. The control circuit allows switching the connecting combinations when the semiconductor device tests in a test mode. The control circuit prohibits switching the connecting combinations in a non-test mode. The switch circuit connects between each of m of the internal voltage generating circuits and each of n of the load circuits through a connecting combination which is selected, based on the control signal, from mn of the connecting combinations.

Abstract: A semiconductor memory device executes a refresh operation on memory banks, and includes: a command decoder that decodes a command from outside the semiconductor memory device, and outputs a refresh instruction when the command is an auto-refresh command; a refresh command generating unit that outputs a refresh command signal by a predetermined number of times corresponding to the number of word lines to be refreshed in response to the refresh instruction; a bank address counter that holds a bank address for selecting a memory bank to be refreshed, counts up the bank address every time the refresh command signal is output, and performs a carry-over action when count-up operations equivalent to the number of the memory banks are performed; and a row address counter that holds a row address for selecting a word line to be refreshed, and counts up the row address in response to the carry-over action.

Abstract: A semiconductor memory device executes a refresh operation on memory banks, and includes: a command decoder that decodes a command from outside the semiconductor memory device, and outputs a refresh instruction when the command is an auto-refresh command; a refresh command generating unit that outputs a refresh command signal by a predetermined number of times corresponding to the number of word lines to be refreshed in response to the refresh instruction; a refresh address counter that counts up an address designating a memory bank and a word line every time the refresh command signal is output; and a refresh number controller that controls the number of times that refresh command signals are output so that each memory bank is refreshed and, after a count value for designating the word line of the refresh address counter has been changed, at least one of the memory banks is further refreshed.

Abstract: A semiconductor memory device includes first and second column selection signal lines, first bit lines being and second bit lines. The first bit lines are associated with the first column selection signal line. The second bit lines are associated with the second column lines. At least one of the first bit lines is positioned between two of the second bit lines.

Abstract: A semiconductor memory device simultaneously selects an object cell and a counter cell which connect with a common bit line, simultaneously activates sub-word lines of the object cell and the counter cell after predetermined levels are written in the object cell and the counter cell, simultaneously read data of the object cell and the counter cell from the common bit line, and hence, determines whether the object cell is normal or defective, based on a voltage level of the common bit line. Thereby, the defective cell in the semiconductor memory device can be reliably detected.

Abstract: A termination circuit that adjusts differences in the resistance values of wiring-layer resistance and transistor ON resistance so that a desired termination resistance value is obtained. A wiring-layer resistance 10 is connected between an input terminal 30, which connects to an input circuit 18, and a first node; a transistor group 12 is connected between the first node and ground; a wiring-layer resistance 11 is connected between the first node and a second node; and a transistor group 13 is connected between the second node and ground. Furthermore, a wiring-layer resistance 14 is connected between the input terminal 30 and a third node; a transistor group 16 is connected between the third node and power source VDD; a wiring-layer resistance 15 is connected between the third node and a fourth node, and a transistor group 17 is connected between a fourth node and power source VDD.

Abstract: A semiconductor memory device executes a refresh operation on memory banks, and includes: a command decoder that decodes a command from outside the semiconductor memory device, and outputs a refresh instruction when the command is an auto-refresh command; a refresh command generating unit that outputs a refresh command signal by a predetermined number of times corresponding to the number of word lines to be refreshed in response to the refresh instruction; a bank address counter that holds a bank address for selecting a memory bank to be refreshed, counts up the bank address every time the refresh command signal is output, and performs a carry-over action when count-up operations equivalent to the number of the memory banks are performed; and a row address counter that holds a row address for selecting a word line to be refreshed, and counts up the row address in response to the carry-over action.

Abstract: A semiconductor memory device includes first and second column selection signal lines, first bit lines being and second bit lines. The first bit lines are associated with the first column selection signal line. The second bit lines are associated with the second column lines. At least one of the first bit lines is positioned between two of the second bit lines.

Abstract: A termination circuit that adjusts differences in the resistance values of wiring-layer resistance and transistor ON resistance so that a desired termination resistance value is obtained. A wiring-layer resistance 10 is connected between an input terminal 30, which connects to an input circuit 18, and a first node; a transistor group 12 is connected between the first node and ground; a wiring-layer resistance 11 is connected between the first node and a second node; and a transistor group 13 is connected between the second node and ground. Furthermore, a wiring-layer resistance 14 is connected between the input terminal 30 and a third node; a transistor group 16 is connected between the third node and power source VDD; a wiring-layer resistance 15 is connected between the third node and a fourth node, and a transistor group 17 is connected between a fourth node and power source VDD.

Abstract: A boosting circuit includes first to third charge pump circuits and a switching unit. The first to third charge pump circuit which contains first to third capacitive section charged to the first voltage, respectively. The switching unit connects the first charge pump circuit and the second charge pump circuit in series in response to a first switch signal and a control signal such that a second voltage higher than the first voltage is outputted from a first node to a first internal circuit of a semiconductor device. Also, the switching unit connects the first charge pump circuit, the second charge pump circuit and the third charge pump circuit in series in response to a second switch signal and the control signal, such that a third voltage is outputted from a second node to a second internal circuit of the semiconductor device.

Abstract: A boosting circuit includes first to third charge pump circuits and a switching unit. The first to third charge pump circuit which contains first to third capacitive section charged to the first voltage, respectively. The switching unit connects the first charge pump circuit and the second charge pump circuit in series in response to a first switch signal and a control signal such that a second voltage higher than the first voltage is outputted from a first node to a first internal circuit of a semiconductor device. Also, the switching unit connects the first charge pump circuit, the second charge pump circuit and the third charge pump circuit in series in response to a second switch signal and the control signal, such that a third voltage is outputted from a second node to a second internal circuit of the semiconductor device.

Abstract: A semiconductor memory device including a plurality of normal memory cells (11) and redundant memory cells (12) is disclosed. Normal memory cells (11) may include true normal memory cells and complement normal memory cells. Redundant memory cells (12) may include true redundant memory cells and complement redundant memory cells. When a normal memory cell (11) is found to be a defective memory cell, it may be replaced by a replacement redundant memory cell from the plurality of redundant memory cells (12). A defective memory cell that is a true normal memory cell may be replaced with a replacement memory cell that is a true redundant memory cell and a defective memory cell that is a complement memory cell may be replaced with a replacement memory cell that is a complement redundant memory cell. In this way, electric and physical conditions of a replacement memory cell may be essentially the same as the electric and physical conditions of the defective memory cell would have been had it not been replaced.

Abstract: A semiconductor memory device including a plurality of normal memory cells (11) and redundant memory cells (12) is disclosed. Normal memory cells (11) may include true normal memory cells and complement normal memory cells. Redundant memory cells (12) may include true redundant memory cells and complement redundant memory cells. When a normal memory cell (11) is found to be a defective memory cell, it may be replaced by a replacement redundant memory cell from the plurality of redundant memory cells (12). A defective memory cell that is a true normal memory cell may be replaced with a replacement memory cell that is a true redundant memory cell and a defective memory cell that is a complement memory cell may be replaced with a replacement memory cell that is a complement redundant memory cell. In this way, electric and physical conditions of a replacement memory cell may be essentially the same as the electric and physical conditions of the defective memory cell would have been had it not been replaced.

Abstract: Write switch signal output circuits for outputting write switch signals for controlling the turning-on/off of transfer gates for interconnecting digit lines and write data lines are supplied with a write enable signal that controls write timing and pairs of complementary write data signals outputted from write data output circuits. When the write data output circuits are inactive, the write switch signal output circuits inactivate the write switch signals because the paired complementary write data signals are of a precharged potential level. When the write data output circuits are active, the write switch signal output circuits activate the write switch signals when the write enable signal is active because write data is outputted as the paired complementary write data signals.