Patents by Inventor Gen P. Lauer
Gen P. Lauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11011698Abstract: A magnetic memory device includes a magnetic memory stack including a bottom electrode and having a hard mask formed thereon. An encapsulation layer is formed over sides of the magnetic memory stack and has a thickness adjacent to the sides formed on the bottom electrode. A dielectric material is formed over the encapsulation layer and is removed from over the hard mask and gapped apart from the encapsulation layer on the sides of the magnetic memory stack to form trenches between the dielectric material and the encapsulation layer at the sides of the magnetic memory stack. A top electrode is formed over the hard mask and in the trenches such that the top electrode is spaced apart from the bottom electrode by at least the thickness.Type: GrantFiled: April 14, 2017Date of Patent: May 18, 2021Assignee: International Business Machines CorporationInventors: Anthony J. Annunziata, Gen P. Lauer, Nathan P. Marchack
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Patent number: 10497862Abstract: A magnetic memory device includes a magnetic memory stack including a bottom electrode and having a hard mask formed thereon. An encapsulation layer is formed over sides of the magnetic memory stack and has a thickness adjacent to the sides formed on the bottom electrode. A dielectric material is formed over the encapsulation layer and is removed from over the hard mask and gapped apart from the encapsulation layer on the sides of the magnetic memory stack to form trenches between the dielectric material and the encapsulation layer at the sides of the magnetic memory stack. A top electrode is formed over the hard mask and in the trenches such that the top electrode is spaced apart from the bottom electrode by at least the thickness.Type: GrantFiled: June 29, 2018Date of Patent: December 3, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Annunziata, Gen P. Lauer, Nathan P. Marchack
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Patent number: 10388857Abstract: A magnetoresistive memory cell includes a magnetic tunnel junction pillar having a circular cross section. The pillar has a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer. A first conductive contact is disposed above the magnetic tunnel junction pillar. A second conductive contact is disposed below the magnetic tunnel junction pillar.Type: GrantFiled: June 16, 2016Date of Patent: August 20, 2019Assignee: International Business Machines CorporationInventors: Anthony J. Annunziata, Armand A. Galan, Steve Holmes, Eric A. Joseph, Gen P. Lauer, Qinghuang Lin, Nathan P. Marchack
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Patent number: 10256397Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.Type: GrantFiled: February 27, 2018Date of Patent: April 9, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Annunziata, Gen P. Lauer, Janusz J. Nowak, Eugene J. O'Sullivan
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Patent number: 10243138Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.Type: GrantFiled: February 27, 2018Date of Patent: March 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Annunziata, Gen P. Lauer, Janusz J. Nowak, Eugene J. O'Sullivan
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Patent number: 10170698Abstract: A method of forming a pillar includes masking a photoresist material using a reticle and a developer having a polarity opposite that of the photoresist to provide an island of photoresist material. A layer under the island of photoresist material is etched to establish a pillar defined by the island of photoresist material.Type: GrantFiled: May 9, 2017Date of Patent: January 1, 2019Inventors: Anthony J. Annunziata, Armand A. Galan, Steve Holmes, Eric A. Joseph, Gen P. Lauer, Qinghuang Lin, Nathan P. Marchack
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Patent number: 10170609Abstract: A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain regions. At least one nanowire has a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the nanowire is suspended above the wafer in the gate region. At least one gate electrode is in the gate region. The gate electrode contacts an entire surface of the nanowire to define a gate-all-around configuration. At least one pair of oxidized spacers surrounds the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions.Type: GrantFiled: November 23, 2015Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Szu-Lin Cheng, Michael A. Guillorn, Gen P. Lauer, Isaac Lauer
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Patent number: 10170608Abstract: A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain regions. At least one nanowire has a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the nanowire is suspended above the wafer in the gate region. At least one gate electrode is in the gate region. The gate electrode contacts an entire surface of the nanowire to define a gate-all-around configuration. At least one pair of oxidized spacers surrounds the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions.Type: GrantFiled: June 30, 2015Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Szu-Lin Cheng, Michael A. Guillorn, Gen P. Lauer, Isaac Lauer
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Publication number: 20180309053Abstract: A magnetic memory device includes a magnetic memory stack including a bottom electrode and having a hard mask formed thereon. An encapsulation layer is formed over sides of the magnetic memory stack and has a thickness adjacent to the sides formed on the bottom electrode. A dielectric material is formed over the encapsulation layer and is removed from over the hard mask and gapped apart from the encapsulation layer on the sides of the magnetic memory stack to form trenches between the dielectric material and the encapsulation layer at the sides of the magnetic memory stack. A top electrode is formed over the hard mask and in the trenches such that the top electrode is spaced apart from the bottom electrode by at least the thickness.Type: ApplicationFiled: June 29, 2018Publication date: October 25, 2018Inventors: Anthony J. Annunziata, Gen P. Lauer, Nathan P. Marchack
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Patent number: 10084127Abstract: A magnetic memory device includes a magnetic memory stack including a bottom electrode and having a hard mask formed thereon. An encapsulation layer is formed over sides of the magnetic memory stack and has a thickness adjacent to the sides formed on the bottom electrode. A dielectric material is formed over the encapsulation layer and is removed from over the hard mask and gapped apart from the encapsulation layer on the sides of the magnetic memory stack to form trenches between the dielectric material and the encapsulation layer at the sides of the magnetic memory stack. A top electrode is formed over the hard mask and in the trenches such that the top electrode is spaced apart from the bottom electrode by at least the thickness.Type: GrantFiled: April 14, 2017Date of Patent: September 25, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Annunziata, Gen P. Lauer, Nathan P. Marchack
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Publication number: 20180190901Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.Type: ApplicationFiled: February 27, 2018Publication date: July 5, 2018Inventors: Anthony J. Annunziata, Gen P. Lauer, Janusz J. Nowak, Eugene J. O'Sullivan
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Publication number: 20180190900Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.Type: ApplicationFiled: February 27, 2018Publication date: July 5, 2018Inventors: Anthony J. Annunziata, Gen P. Lauer, Janusz J. Nowak, Eugene J. O'Sullivan
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Patent number: 9960347Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.Type: GrantFiled: April 27, 2017Date of Patent: May 1, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Annunziata, Gen P. Lauer, Janusz J. Nowak, Eugene J. O'Sullivan
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Patent number: 9954063Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.Type: GrantFiled: April 20, 2016Date of Patent: April 24, 2018Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Gen P. Lauer, Isaac Lauer, Jeffrey W. Sleight
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Patent number: 9954062Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.Type: GrantFiled: April 20, 2016Date of Patent: April 24, 2018Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Gen P. Lauer, Isaac Lauer, Jeffrey W. Sleight
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Patent number: 9947863Abstract: A method of making a magnetic random access memory (MRAM) device includes depositing a spacer material on an electrode; forming a magnetic tunnel junction (MTJ) on the spacer material that includes a reference layer in contact with the spacer material, a free layer, and a tunnel barrier layer; patterning a hard mask on the free layer; etching the MTJ and the spacer material to transfer a pattern of the hard mask into the MTJ and the spacer material; forming an insulating layer along a sidewall of the hard mask, the MTJ, and the spacer material; disposing an interlayer dielectric (ILD) on and around the hard mask, MTJ, and spacer material; etching through the ILD to form a trench that extends to a surface and sidewall of the hard mask and a sidewall of a portion of the MTJ; and disposing a metal in the trench to form a contact electrode.Type: GrantFiled: April 21, 2017Date of Patent: April 17, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Annunziata, Gen P. Lauer, Nathan P. Marchack
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Patent number: 9859375Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.Type: GrantFiled: April 20, 2016Date of Patent: January 2, 2018Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Gen P. Lauer, Isaac Lauer, Jeffrey W. Sleight
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Patent number: 9853210Abstract: A method of making a magnetic random access memory (MRAM) device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer positioned in contact with the electrode, a free layer, and a tunnel barrier layer arranged between the reference layer and the free layer; and depositing an encapsulating layer on and along sidewalls of the MTJ by physical sputtering or ablation of a target material onto the MTJ.Type: GrantFiled: November 17, 2015Date of Patent: December 26, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Annunziata, Gen P. Lauer, Nathan P. Marchack, Stephen M. Rossnagel
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Patent number: 9812370Abstract: In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.Type: GrantFiled: October 24, 2016Date of Patent: November 7, 2017Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Gen P. Lauer, Isaac Lauer, Jeffrey W. Sleight
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Patent number: 9748310Abstract: A method of making a magnetic random access memory (MRAM) device includes depositing a spacer material on an electrode; forming a magnetic tunnel junction (MTJ) on the spacer material that includes a reference layer in contact with the spacer material, a free layer, and a tunnel barrier layer; patterning a hard mask on the free layer; etching the MTJ and the spacer material to transfer a pattern of the hard mask into the MTJ and the spacer material; forming an insulating layer along a sidewall of the hard mask, the MTJ, and the spacer material; disposing an interlayer dielectric (ILD) on and around the hard mask, MTJ, and spacer material; etching through the ILD to form a trench that extends to a surface and sidewall of the hard mask and a sidewall of a portion of the MTJ; and disposing a metal in the trench to form a contact electrode.Type: GrantFiled: October 7, 2016Date of Patent: August 29, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Annunziata, Gen P. Lauer, Nathan P. Marchack