Patents by Inventor Gen Tada
Gen Tada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9401319Abstract: A semiconductor device is provided, in which a first lead (11) is joined with the bottom electrode (23) of a MOS-FET (21) with first solder (51), the top electrode (22) of the MOS-FET is joined with an internal lead (31) with second solder (52), the internal lead is joined with a projection (61) of a second lead with third solder (53), and the first lead, second lead, MOS-FET and internal lead are integrally molded using sealing resin (41), wherein the first solder and second solder include support members (54) and (55), respectively, located thereinside and positions of the internal lead and MOS-FET are stabilized by self-alignment.Type: GrantFiled: June 9, 2011Date of Patent: July 26, 2016Assignee: Mitsubishi Electric CorporationInventors: Takuya Oga, Kazuyasu Sakamoto, Tsuyoshi Sugihara, Masaki Kato, Daisuke Nakashima, Tsuyoshi Jida, Gen Tada
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Publication number: 20130307130Abstract: A semiconductor device is provided, in which a first lead (11) is joined with the bottom electrode (23) of a MOS-FET (21) with first solder (51), the top electrode (22) of the MOS-FET is joined with an internal lead (31) with second solder (52), the internal lead is joined with a projection (61) of a second lead with third solder (53), and the first lead, second lead, MOS-FET and internal lead are integrally molded using sealing resin (41), wherein the first solder and second solder include support members (54) and (55), respectively, located thereinside and positions of the internal lead and MOS-FET are stabilized by self-alignment.Type: ApplicationFiled: June 9, 2011Publication date: November 21, 2013Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takuya Oga, Kazuyasu Sakamoto, Tsuyoshi Sugihara, Masaki Kato, Daisuke Nakashima, Tsuyoshi Jida, Gen Tada
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Patent number: 7876291Abstract: A display panel drive device of reduced area occupied by circuit elements. The display panel drive device includes an output stage circuit having a low side selector circuit constituted by connecting in series inverters and a buffer circuit, n-channel IGBTs, a Zener diode and resistance respectively connected between the gate and emitter of the IGBT, a buffer circuit, and a high side selector circuit including an inverter. The buffer circuit includes a high side Pch-MOS operated by a logic signal from the high side selector circuit and a low side Nch-MOS operated by a logic signal of the low side selector circuit.Type: GrantFiled: February 27, 2006Date of Patent: January 25, 2011Assignee: Fuji Electric Systems Co., Ltd.Inventors: Hideto Kobayashi, Gen Tada, Yoshihiro Shigeta, Hiroshi Shimabukuro
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Patent number: 7714363Abstract: Wiring of a PDP address driver IC is disclosed which affords an adequate permitted current capacity. In the PDP address driver IC that drives the PDP, a layer, in which a planar high voltage ground wiring layer and a planar high voltage power wiring layer are formed, is provided atop a layer in which planar high voltage ground wiring layers that supply a ground potential to the active element that is formed within the PDP address driver IC and in which planar high voltage power wiring layers that supply a source potential to the active element are formed. Accordingly, the PDP address driver IC can comprise an adequate permitted current capacity while maintaining a compact size and comprising a multiplicity of output bit portions.Type: GrantFiled: September 25, 2007Date of Patent: May 11, 2010Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Takahiro Nomiyama, Gen Tada, Yoshihiro Shigeta
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Patent number: 7687385Abstract: The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region.Type: GrantFiled: March 2, 2007Date of Patent: March 30, 2010Assignee: Fuji Electric Holdings Co., Ltd.Inventors: Kazuo Matsuzaki, Naoto Fujishima, Akio Kitamura, Gen Tada, Masaru Saito
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Patent number: 7606082Abstract: The semiconductor circuit includes a voltage-controlled semiconductor device (N)N, the resistance value of which is controllable with a high voltage, the drain terminal of the N can be connected to the gate terminal (control terminal) of an output semiconductor device (NO) via a resistor (R) or to a last output stage of the driver circuit, the source terminal of the N is connected to the emitter terminal of the NO, and the gate terminal of the N is connected to the collector terminal, which is the output terminal, of the NO. When the input terminal of the semiconductor circuit is at the Hi-level, the NO OFF. By connecting the output terminal of the NO to the high-potential-side of a high-voltage circuit disposed separately and the negative electrode of a control power supply (VDD) to the low-potential-side of the high-voltage circuit in the state, in which the NO is OFF, a desired high voltage is applied between the collector and emitter of the NO.Type: GrantFiled: September 14, 2006Date of Patent: October 20, 2009Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Hiroshi Shimabukuro, Hideto Kobayashi, Yoshihiro Shigeta, Gen Tada
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Publication number: 20080083937Abstract: Wiring of a PDP address driver IC is disclosed which affords an adequate permitted current capacity. In the PDP address driver IC that drives the PDP, a layer, in which a planar high voltage ground wiring layer and a planar high voltage power wiring layer are formed, is provided atop a layer in which planar high voltage ground wiring layers that supply a ground potential to the active element that is formed within the PDP address driver IC and in which planar high voltage power wiring layers that supply a source potential to the active element are formed. Accordingly, the PDP address driver IC can comprise an adequate permitted current capacity while maintaining a compact size and comprising a multiplicity of output bit portions.Type: ApplicationFiled: September 25, 2007Publication date: April 10, 2008Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Takahiro NOMIYAMA, Gen TADA, Yoshihiro SHIGETA
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Publication number: 20070155144Abstract: The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region.Type: ApplicationFiled: March 2, 2007Publication date: July 5, 2007Applicant: FUJI ELECTRIC HOLDING CO., LTD.Inventors: Kazuo Matsuzaki, Naoto Fujishima, Akio Kitamura, Gen Tada, Masaru Saito
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Patent number: 7195980Abstract: The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region.Type: GrantFiled: January 6, 2005Date of Patent: March 27, 2007Assignee: Fuji Electric Co., Ltd.Inventors: Kazuo Matsuzaki, Naoto Fujishima, Akio Kitamura, Gen Tada, Masaru Saito
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Publication number: 20070064476Abstract: The semiconductor circuit includes a voltage-controlled semiconductor device (N)N, the resistance value of which is controllable with a high voltage, the drain terminal of the N can be connected to the gate terminal (control terminal) of an output semiconductor device (NO) via a resistor (R) or to a last output stage of the driver circuit, the source terminal of the N is connected to the emitter terminal of the NO, and the gate terminal of the N is connected to the collector terminal, which is the output terminal, of the NO. When the input terminal of the semiconductor circuit is at the Hi-level, the NO OFF. By connecting the output terminal of the NO to the high-potential-side of a high-voltage circuit disposed separately and the negative electrode of a control power supply (VDD) to the low-potential-side of the high-voltage circuit in the state, in which the NO is OFF, a desired high voltage is applied between the collector and emitter of the NO.Type: ApplicationFiled: September 14, 2006Publication date: March 22, 2007Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Hiroshi SHIMABUKURO, Hideto KOBAYASHI, Yoshihiro SHIGETA, Gen TADA
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Patent number: 7173454Abstract: A display device driver circuit includes a timer circuit 20 that outputs to output stage circuits 10 a control signal for turning off IGBTs 11 and 12 when a next clock signal is not inputted to the timer circuit 20 for a predetermined period of time, and the output stage circuits 10 turn off the IGBTs 11 and 12 to put the output terminals DO thereof into a high impedance state so that an overcurrent may be prevented from flowing through the IGBTs 11 and 12.Type: GrantFiled: February 23, 2005Date of Patent: February 6, 2007Assignee: Fuji Electric Device Technology Co., LtdInventors: Hideto Kobayashi, Gen Tada, Yoshihiro Shigeta, Hiroshi Shimabukuro
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Publication number: 20060223254Abstract: A display panel drive device of reduced area occupied by circuit elements. The display panel drive device includes an output stage circuit having a low side selector circuit constituted by connecting in series inverters and a buffer circuit, n-channel IGBTs, a Zener diode and resistance respectively connected between the gate and emitter of the IGBT, a buffer circuit, and a high side selector circuit including an inverter. The buffer circuit includes a high side Pch-MOS operated by a logic signal from the high side selector circuit and a low side Nch-MOS operated by a logic signal of the low side selector circuit.Type: ApplicationFiled: February 27, 2006Publication date: October 5, 2006Inventors: Hideto Kobayashi, Gen Tada, Yoshihiro Shigeta, Hiroshi Shimabukuro
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Publication number: 20050195179Abstract: A display device driver circuit includes a timer circuit 20 that outputs to output stage circuits 10 a control signal for turning off IGBTs 11 and 12 when a next clock signal is not inputted to the timer circuit 20 for a predetermined period of time, and the output stage circuits 10 turn off the IGBTs 11 and 12 to put the output terminals Do thereof into a high impedance state so that an overcurrent may be prevented from flowing through the IGBTs 11 and 12.Type: ApplicationFiled: February 23, 2005Publication date: September 8, 2005Inventors: Hideto Kobayashi, Gen Tada, Yoshihiro Shigeta, Hiroshi Shimabukuro
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Publication number: 20050127439Abstract: The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region.Type: ApplicationFiled: January 6, 2005Publication date: June 16, 2005Inventors: Kazuo Matsuzaki, Naoto Fujishima, Akio Kitamura, Gen Tada, Masaru Saito
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Patent number: 6853034Abstract: The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region.Type: GrantFiled: January 9, 2001Date of Patent: February 8, 2005Assignee: Fuji Electric Co., Ltd.Inventors: Kazuo Matsuzaki, Naoto Fujishima, Akio Kitamura, Gen Tada, Masaru Saito
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Patent number: 6844598Abstract: A film thickness of a gate oxide film of a lateral high breakdown voltage MOSFET of a first conduction type is formed with a thickness in which an electric field value to an absolute maximum rated voltage between a source and a drain becomes equal to or less than 4 MV/cm, and a drain diffused layer is formed so that a total amount of impurities therein becomes equal to or more than 2×1012/cm2 to reduce an on-resistance of the lateral high breakdown voltage MOSFET while ensuring a breakdown voltage thereof, and to reduce an area of the lateral high breakdown voltage MOSFET.Type: GrantFiled: February 18, 2004Date of Patent: January 18, 2005Assignee: Fuji Electric Co., Ltd.Inventors: Gen Tada, Masaru Saito
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Patent number: 6818954Abstract: A film thickness of a gate oxide film of a lateral high breakdown voltage MOSFET of a first conduction type is formed with a thickness in which an electric field value to an absolute maximum rated voltage between a source and a drain becomes equal to or less than 4 MV/cm, and a drain diffused layer is formed so that a total amount of impurities therein becomes equal to or more than 2×1012/cm2 to reduce an on-resistance of the lateral high breakdown voltage MOSFET while ensuing a breakdown voltage thereof, and to reduce an area of the lateral high breakdown voltage MOSFET.Type: GrantFiled: December 3, 2002Date of Patent: November 16, 2004Assignee: Fuji Electric Co., Ltd.Inventors: Gen Tada, Masaru Saito
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Publication number: 20040159856Abstract: A film thickness of a gate oxide film of a lateral high breakdown voltage MOSFET of a first conduction type is formed with a thickness in which an electric field value to an absolute maximum rated voltage between a source and a drain becomes equal to or less than 4 MV/cm, and a drain diffused layer is formed so that a total amount of impurities therein becomes equal to or more than 2×1012/cm2 to reduce an on-resistance of the lateral high breakdown voltage MOSFET while ensuring a breakdown voltage thereof, and to reduce an area of the lateral high breakdown voltage MOSFET.Type: ApplicationFiled: February 18, 2004Publication date: August 19, 2004Applicant: Fuji Electric Co., Ltd.Inventors: Gen Tada, Masaru Saito
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Patent number: 6740952Abstract: A semiconductor device includes a stable high withstand voltage lateral MISFET device which suppresses a gradual withstand voltage drop under high voltage and humidity conditions. In a MISFET device with a 700V breakdown drain voltage, the length of extension Mc (&mgr;m) of a field plate FP1 from the source side end of a thermal oxidization film, and the total insulating film thickness Tox (&mgr;m) directly below the extending tip of the field plate FP1, are greater than or equal to lower limit values Mcmin, Tcmin. As a result, even if there is growth in charge accumulation at the interface of the mold resin, the field strength at a point B and point C is always lower than at a point A, which suppresses a gradual withstand voltage drop and a gradual ON current drop, whereby it becomes possible to realize a withstand voltage of 700V.Type: GrantFiled: March 12, 2002Date of Patent: May 25, 2004Assignee: Fuji Electric Co., Ltd.Inventors: Naoto Fujishima, Akio Kitamura, Gen Tada, Masaru Saito
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Publication number: 20030122195Abstract: A film thickness of a gate oxide film of a lateral high breakdown voltage MOSFET of a first conduction type is formed with a thickness in which an electric field value to an absolute maximum rated voltage between a source and a drain becomes equal to or less than 4 MV/cm, and a drain diffused layer is formed so that a total amount of impurities therein becomes equal to or more than 2×1012/cm2 to reduce an on-resistance of the lateral high breakdown voltage MOSFET while ensuring a breakdown voltage thereof, and to reduce an area of the lateral high breakdown voltage MOSFET.Type: ApplicationFiled: December 3, 2002Publication date: July 3, 2003Applicant: Fuji Electric Co., Ltd.Inventors: Gen Tada, Masaru Saito