Patents by Inventor Genadi TVERSKOY

Genadi TVERSKOY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Local bit select with improved fast read before write suppression
    Patent number: 11682452
    Abstract: Aspects of the invention include a first pull-down device and a second pull-down device, wherein a first drain terminal is connected to a second source terminal, and wherein a first gate terminal is connected to a true read local bitline, wherein a second drain terminal is connected to a compliment read local bit line, and wherein a second gate terminal is connected to a true write global bitline, a third pull-down device and a fourth pull-down device, wherein a third source terminal is connected to the voltage supply, wherein a third drain terminal is connected to a fourth source terminal, and wherein a third gate terminal is connected to the compliment read local bitline, and wherein a fourth drain terminal is connected to the true read local bitline, and wherein a fourth gate terminal is connected to a compliment write global bit line.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: June 20, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Antonio Pelella, Dongho Lee, Genadi Tverskoy, Zhiying Chen, Brian James Yavoich
  • LOCAL BIT SELECT WITH IMPROVED FAST READ BEFORE WRITE SUPPRESSION
    Publication number: 20230086799
    Abstract: Aspects of the invention include a first pull-down device and a second pull-down device, wherein a first drain terminal is connected to a second source terminal, and wherein a first gate terminal is connected to a true read local bitline, wherein a second drain terminal is connected to a compliment read local bit line, and wherein a second gate terminal is connected to a true write global bitline, a third pull-down device and a fourth pull-down device, wherein a third source terminal is connected to the voltage supply, wherein a third drain terminal is connected to a fourth source terminal, and wherein a third gate terminal is connected to the compliment read local bitline, and wherein a fourth drain terminal is connected to the true read local bitline, and wherein a fourth gate terminal is connected to a compliment write global bit line.
    Type: Application
    Filed: September 21, 2021
    Publication date: March 23, 2023
    Inventors: Antonio PELELLA, Dongho LEE, Genadi TVERSKOY, Zhiying CHEN, Brian James YAVOICH