Abstract: A die seal structure having trenches is provided. The die seal structure is formed on a silicon substrate and used to prevent lateral stress from causing damage to internal circuits in a die when a wafer is being cutted. A die seal comprises a buffer area, a seal ring and a buffer space. The buffer area is adjacent to the internal circuit. The buffer space is adjacent to a scribe line. The seal ring having a structure of stacked metal layers and dielectric layers is located between the buffer area and the buffer space. A trench for enhancing the stress-protection ability of the die seal is formed in the buffer space. The trench is formed by wet-etching SiO2 residues on the buffer space using buffered HF, or wet-etching Si3N4 residues on the buffer space using phosphoric acid at 180° C. In addition, a portion of the substrate may be removed by wet etching using HNO3 and HF. Dry etching may also be used to remove the dielectric residues and a portion of the silicon substrate on the buffer space.

Abstract: The present invention provides a method of fabricating a die seal. The die seal comprises a buffer area being adjacent to a die, a buffer space being adjacent to a scribe line, and a seal ring located between the buffer area and the buffer space. The seal ring is stacked by at least one metal layer and at least one dielectric layer. A passivation layer is formed and covers entire the die seal. The method comprises forming an amorphous silicon film on a top metal layer prior to the step of forming the passivation layer, and removing the dielectric layer on the buffer space by applying the amorphous silicon film as an etch stop layer in the step of etching the passivation layer to enhance the robustness of the die seal from damage by a lateral stress when a wafer is sawed. When the dielectric layer is made of SiO.sub.2, a plasma containing CF.sub.4 and H.sub.2. can be utilized in the step of etching the passivation layer. Because the plasma has an extremely high etching selectivity ratio, the SiO.sub.

Abstract: A die seal structure for a small-dimension semiconductor integrated circuit is disclosed. The die seal structure, which lies between an integrated circuit region and a scribe line over a semiconductor wafer, includes at least one dielectric layer over the semiconductor wafer. At least one contact window is formed in the dielectric layer. The die seal structure further includes at least one plug each filled in one of the contact windows.

Abstract: A method for forming a gate-side air-gap structure in a salicide process for preventing bridging, which starts on a semiconductor wafer with active region defined completely by field oxide, includes the steps: depositing sequentially a thin oxide layer, a polysilicon layer, and a first layer over the wafer; patterning the first layer, the polysilicon layer, and the thin oxide layer to form a stack gate which consists of first layer and a gate, wherein the gate consists of the polysilicon layer and the thin oxide layer; forming lightly-doped drains beside the stack gate in the active region; forming a second layer on the sidewall of the stack gate; forming a spacer on the sidewall of the second layer; forming source and drain regions; removing the first layer and the second layer to reveal the gate, wherein air gaps exist between the gate and the spacer; depositing a titanium layer over the wafer; heating the titanium layer to form TiSi.sub.