Patents by Inventor Gene Leung
Gene Leung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10672368Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.Type: GrantFiled: February 14, 2019Date of Patent: June 2, 2020Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Ryan Scott Haraden, Tolga Ozguner, Adam James Muff, Jeffrey Powers Bradford, Christopher Jon Johnson, Gene Leung, Miguel Comparan
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Patent number: 10514753Abstract: Optimizations are provided for late stage reprojection processing for a multi-layered scene. A multi-layered scene is generated. Late stage reprojection processing is applied to a first layer and different late stage reprojection processing is applied to a second layer. The late stage reprojection processing that is applied to the second layer includes one or more transformations that are applied to the second layer. After the late stage reprojection processing on the various layers is complete, a unified layer is created by compositing the layers together. Then, the render the unified layer is rendered.Type: GrantFiled: March 27, 2017Date of Patent: December 24, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Ryan Scott Haraden, Jeffrey Powers Bradford, Miguel Comparan, Adam James Muff, Gene Leung, Tolga Ozguner
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Patent number: 10410349Abstract: Optimizations are provided for late stage reprojection processing for a multi-layered scene. A scene is generated, which is based on a predicted pose of a portion of a computer system. A sub-region is identified within one of the layers and is isolated from the other regions in the scene. Thereafter, late stage reprojection processing is applied to that sub-region selectively/differently than other regions in the scene that do not undergo the same late state reprojection processing.Type: GrantFiled: March 27, 2017Date of Patent: September 10, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Ryan Scott Haraden, Jeffrey Powers Bradford, Miguel Comparan, Adam James Muff, Gene Leung, Tolga Ozguner
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Patent number: 10338816Abstract: Techniques for controlling access to a memory are provided. The techniques may include receiving and storing output pixel data in a buffer, providing the stored output pixel data to a display controller, receiving stored output pixel data from the buffer at the display controller, switching to a second operating mode state based at least on an amount of available data in the buffer being less than or equal to a threshold, identifying a portion of the image data stored in a memory device for use in generating output pixel data for an updated image, and, in response to operating in the second operating mode, generating the output pixel data without issuing a memory read command via an interconnect to retrieve the portion of the initial image while operating in the second operating mode, and providing the output pixel data to the buffer.Type: GrantFiled: October 8, 2018Date of Patent: July 2, 2019Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Tolga Ozguner, Ishan Jitendra Bhatt, Miguel Comparan, Ryan Scott Haraden, Jeffrey Powers Bradford, Gene Leung
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Publication number: 20190189089Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.Type: ApplicationFiled: February 14, 2019Publication date: June 20, 2019Inventors: Ryan Scott HARADEN, Tolga OZGUNER, Adam James MUFF, Jeffrey Powers BRADFORD, Christopher Jon JOHNSON, Gene LEUNG, Miguel COMPARAN
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Patent number: 10255891Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.Type: GrantFiled: April 12, 2017Date of Patent: April 9, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Ryan Scott Haraden, Tolga Ozguner, Adam James Muff, Jeffrey Powers Bradford, Christopher Jon Johnson, Gene Leung, Miguel Comparan
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Patent number: 10241470Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data.Type: GrantFiled: May 15, 2018Date of Patent: March 26, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Tolga Ozguner, Gene Leung, Jeffrey Powers Bradford, Adam James Muff, Miguel Comparan, Ryan Scott Haraden, Christopher Jon Johnson
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Patent number: 10242654Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power.Type: GrantFiled: January 25, 2017Date of Patent: March 26, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Tolga Ozguner, Jeffrey Powers Bradford, Miguel Comparan, Gene Leung, Adam James Muff, Ryan Scott Haraden, Christopher Jon Johnson
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Publication number: 20190050149Abstract: Techniques for controlling access to a memory are provided. The techniques may include receiving and storing output pixel data in a buffer, providing the stored output pixel data to a display controller, receiving stored output pixel data from the buffer at the display controller, switching to a second operating mode state based at least on an amount of available data in the buffer being less than or equal to a threshold, identifying a portion of the image data stored in a memory device for use in generating output pixel data for an updated image, and, in response to operating in the second operating mode, generating the output pixel data without issuing a memory read command via an interconnect to retrieve the portion of the initial image while operating in the second operating mode, and providing the output pixel data to the buffer.Type: ApplicationFiled: October 8, 2018Publication date: February 14, 2019Applicant: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Tolga OZGUNER, Ishan Jitendra BHATT, Miguel COMPARAN, Ryan Scott HARADEN, Jeffrey Powers BRADFORD, Gene LEUNG
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Publication number: 20180301125Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.Type: ApplicationFiled: April 12, 2017Publication date: October 18, 2018Inventors: Ryan Scott Haraden, Tolga Ozguner, Adam James Muff, Jeffrey Powers Bradford, Christopher Jon Johnson, Gene Leung, Miguel Comparan
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Patent number: 10095408Abstract: Systems and methods for controlling access to a memory are provided. The system may include a buffer to store output data generated by a processing module, and provide the output data to a real-time module, and a buffer monitoring circuit to output an underflow approaching state indication in response to an amount of available data in the buffer being less than or equal to a threshold. The system may include a memory access module arranged to receive memory requests issued by the processing module, and configured to, while operating in a first mode, respond to memory requests with corresponding data retrieved from the memory, switch to operating in a second mode in response to receiving the underflow approaching state indication, and in response to operating in the second mode, respond to memory requests indicating the memory access module did not attempt to retrieve corresponding data from the memory.Type: GrantFiled: March 10, 2017Date of Patent: October 9, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Tolga Ozguner, Ishan Jitendra Bhatt, Miguel Comparan, Ryan Scott Haraden, Jeffrey Powers Bradford, Gene Leung
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Publication number: 20180276824Abstract: Optimizations are provided for late stage reprojection processing for a multi-layered scene. A scene is generated, which is based on a predicted pose of a portion of a computer system. A sub-region is identified within one of the layers and is isolated from the other regions in the scene. Thereafter, late stage reprojection processing is applied to that sub-region selectively/differently than other regions in the scene that do not undergo the same late state reprojection processing.Type: ApplicationFiled: March 27, 2017Publication date: September 27, 2018Inventors: Ryan Scott Haraden, Jeffrey Powers Bradford, Miguel Comparan, Adam James Muff, Gene Leung, Tolga Ozguner
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Publication number: 20180275748Abstract: Optimizations are provided for late stage reprojection processing for a multi-layered scene. A multi-layered scene is generated. Late stage reprojection processing is applied to a first layer and different late stage reprojection processing is applied to a second layer. The late stage reprojection processing that is applied to the second layer includes one or more transformations that are applied to the second layer. After the late stage reprojection processing on the various layers is complete, a unified layer is created by compositing the layers together. Then, the render the unified layer is rendered.Type: ApplicationFiled: March 27, 2017Publication date: September 27, 2018Inventors: Ryan Scott Haraden, Jeffrey Powers Bradford, Miguel Comparan, Adam James Muff, Gene Leung, Tolga Ozguner
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Publication number: 20180260931Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data.Type: ApplicationFiled: May 15, 2018Publication date: September 13, 2018Inventors: Tolga OZGUNER, Gene LEUNG, Jeffrey Powers BRADFORD, Adam James MUFF, Miguel COMPARAN, Ryan Scott HARADEN, Christopher Jon JOHNSON
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Publication number: 20180260120Abstract: Systems and methods for controlling access to a memory are provided. The system may include a buffer to store output data generated by a processing module, and provide the output data to a real-time module, and a buffer monitoring circuit to output an underflow approaching state indication in response to an amount of available data in the buffer being less than or equal to a threshold. The system may include a memory access module arranged to receive memory requests issued by the processing module, and configured to, while operating in a first mode, respond to memory requests with corresponding data retrieved from the memory, switch to operating in a second mode in response to receiving the underflow approaching state indication, and in response to operating in the second mode, respond to memory requests indicating the memory access module did not attempt to retrieve corresponding data from the memory.Type: ApplicationFiled: March 10, 2017Publication date: September 13, 2018Applicant: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Tolga Ozguner, Ishan Jitendra Bhatt, Miguel Comparan, Ryan Scott Haraden, Jeffrey Powers Bradford, Gene Leung
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Publication number: 20180211638Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power.Type: ApplicationFiled: January 25, 2017Publication date: July 26, 2018Inventors: Tolga Ozguner, Jeffrey Powers Bradford, Miguel Comparan, Gene Leung, Adam James Muff, Ryan Scott Haraden, Christopher Jon Johnson
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Patent number: 9978118Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data.Type: GrantFiled: January 25, 2017Date of Patent: May 22, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Tolga Ozguner, Gene Leung, Jeffrey Powers Bradford, Adam James Muff, Miguel Comparan, Ryan Scott Haraden, Christopher Jon Johnson
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Patent number: 8099562Abstract: A technique for accessing a memory array includes receiving, from multiple requesters, memory access requests directed to a single port of the memory array. The memory access requests associated with each of the multiple requesters are serviced, based on a priority assigned to each of the multiple requesters, while maintaining a fixed timing for the memory access requests.Type: GrantFiled: January 8, 2008Date of Patent: January 17, 2012Assignee: International Business Machines CorporationInventors: Wayne M. Barrett, Todd A. Greenfield, Gene Leung
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Publication number: 20090177813Abstract: A technique for accessing a memory array includes receiving, from multiple requesters, memory access requests directed to a single port of the memory array. The memory access requests associated with each of the multiple requesters are serviced, based on a priority assigned to each of the multiple requesters, while maintaining a fixed timing for the memory access requests.Type: ApplicationFiled: January 8, 2008Publication date: July 9, 2009Inventors: Wayne M. Barrett, Todd A. Greenfield, Gene Leung
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Publication number: 20060253659Abstract: A method and a virtual port register array are provided for implementing shared access to a register array port by multiple sources simultaneously. A plurality of write data stages is provided for transferring write data to a plurality of register arrays from the multiple sources. A plurality of read data stages is provided for transferring read data from the plurality of register arrays to the multiple sources. A respective multiplexer stage is coupled between the write data stages and the physical write port and the read data stages and the physical read port and clocking is provided to alternate register array access and to allow pass-through of only one source request at a time per physical write port and physical read port.Type: ApplicationFiled: May 5, 2005Publication date: November 9, 2006Applicant: International Business Machines CorporationInventors: Todd Greenfield, Philip Hillier, Gene Leung