Patents by Inventor Gene Sheu
Gene Sheu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11081580Abstract: A high-voltage semiconductor device includes a semiconductor substrate having a first conductivity type, and a first high-voltage well region disposed in the semiconductor substrate and having a second conductivity type that is opposite to the first conductivity type. The high-voltage semiconductor device also includes a first buried layer disposed on the first high-voltage well region and having the first conductivity type, and a second buried layer and a third buried layer disposed on the first high-voltage well region and having the second conductivity type, wherein the first buried layer is between the second buried layer and the third buried layer. The high-voltage semiconductor device further includes a source region and a drain region disposed on the first buried layer and having the second conductivity type.Type: GrantFiled: December 14, 2018Date of Patent: August 3, 2021Assignee: Nuvoton Technology CorporationInventors: Gene Sheu, Vivek Ningaraju, Po-An Chen, Shaik Mastanbasheer, Pooja Ravindra Deshmane, Monika Bharti, Syed Neyaz Imam
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Publication number: 20200044080Abstract: A high-voltage semiconductor device includes a semiconductor substrate having a first conductivity type, and a first high-voltage well region disposed in the semiconductor substrate and having a second conductivity type that is opposite to the first conductivity type. The high-voltage semiconductor device also includes a first buried layer disposed on the first high-voltage well region and having the first conductivity type, and a second buried layer and a third buried layer disposed on the first high-voltage well region and having the second conductivity type, wherein the first buried layer is between the second buried layer and the third buried layer. The high-voltage semiconductor device further includes a source region and a drain region disposed on the first buried layer and having the second conductivity type.Type: ApplicationFiled: December 14, 2018Publication date: February 6, 2020Inventors: Gene SHEU, Vivek NINGARAJU, Po-An CHEN, Shaik MASTANBASHEER, Pooja Ravindra DESHMANE, Monika BHARTI, Syed Neyaz IMAM
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Patent number: 10103279Abstract: A PIN diode is formed on an insulating structure on a substrate of semiconductor. The insulating structure is disposed on a high voltage doped region in the substrate. The PIN diode includes a semiconductor layer, disposed on the insulating structure. The semiconductor layer includes a first doped region of a first conductivity type, at least one second doped region of a second conductivity type, and at least one intrinsic region without being doped or lightly doped between the first doped region and the at least one second doped region. The first conductive type is opposite to the second conductivity type. At least one interconnection structure is disposed on the insulating structure to electrically connect the at least one intrinsic region to the high voltage doped well.Type: GrantFiled: December 29, 2017Date of Patent: October 16, 2018Assignee: Nuvoton Technology CorporationInventors: Vivek Ningaraju, Gene Sheu, Po-An Chen, Subramanya Jayasheela Rao, Aanand, Syed Sarwar Imam
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Publication number: 20180190836Abstract: A PIN diode is formed on an insulating structure on a substrate of semiconductor. The insulating structure is disposed on a high voltage doped region in the substrate. The PIN diode includes a semiconductor layer, disposed on the insulating structure. The semiconductor layer includes a first doped region of a first conductivity type, at least one second doped region of a second conductivity type, and at least one intrinsic region without being doped or lightly doped between the first doped region and the at least one second doped region. The first conductive type is opposite to the second conductivity type. At least one interconnection structure is disposed on the insulating structure to electrically connect the at least one intrinsic region to the high voltage doped well.Type: ApplicationFiled: December 29, 2017Publication date: July 5, 2018Applicant: Nuvoton Technology CorporationInventors: Vivek Ningaraju, Gene Sheu, Po-An Chen, Subramanya Jayasheela Rao, . Aanand, Syed Sarwar Imam
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Patent number: 9466730Abstract: The invention provides a semiconductor device, including: a substrate of a first conductivity type having an active region and a termination region; an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches and second trenches in the epitaxial layer; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer; a source region; an inter-layer dielectric layer; and a contact plug formed on the source region.Type: GrantFiled: January 17, 2014Date of Patent: October 11, 2016Assignee: Vanguard International Semiconductor CorporationInventors: Rahul Kumar, Manoj Kumar, Gene Sheu, Shao-Ming Yang, Rudy Octavius Sihombing, Chia-Hao Lee, Shang-Hui Tu
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Patent number: 9331196Abstract: A semiconductor device including a gate structure, a source region, a drain region, a first conductive type epitaxial layer, a high voltage second conductive type well, a linear graded high voltage first conductive type well and a first conductive type buried layer is provided. The first conductive type buried layer is located within the first conductive type epitaxial layer and below the high voltage second conductive type well, and a length of the first conductive type buried layer is smaller than a length of the high voltage second conductive type well.Type: GrantFiled: October 2, 2014Date of Patent: May 3, 2016Assignee: Nuvoton Technology CorporationInventors: Shao-Ming Yang, Gene Sheu, Antonius Fran Yannu Pramudyo, Erry Dwi Kurniawan
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Publication number: 20160099346Abstract: A semiconductor device including a gate structure, a source region, a drain region, a first conductive type epitaxial layer, a high voltage second conductive type well, a linear graded high voltage first conductive type well and a first conductive type buried layer is provided. The first conductive type buried layer is located within the first conductive type epitaxial layer and below the high voltage second conductive type well, and a length of the first conductive type buried layer is smaller than a length of the high voltage second conductive type well.Type: ApplicationFiled: October 2, 2014Publication date: April 7, 2016Inventors: Shao-Ming Yang, Gene Sheu, Antonius Fran Yannu Pramudyo, Erry Dwi Kurniawan
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Publication number: 20150206966Abstract: The invention provides a semiconductor device, including: a substrate of a first conductivity type having an active region and a termination region; an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches and second trenches in the epitaxial layer; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer; a source region; an inter-layer dielectric layer; and a contact plug formed on the source region.Type: ApplicationFiled: January 17, 2014Publication date: July 23, 2015Applicant: Vanguard International Semiconductor CorporationInventors: Rahul KUMAR, Manoj KUMAR, Gene SHEU, Shao-Ming YANG, Rudy Octavius SIHOMBING, Chia-Hao LEE, Shang-Hui TU
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Patent number: 9048115Abstract: A method for fabricating a semiconductor device is provided. An epitaxial layer is grown on a substrate, wherein the epitaxial layer and the substrate have a first conductivity type. A trench is formed in the epitaxial layer. A barrier region is formed at a bottom of the trench. A doped region of a second conductivity type is formed in the epitaxial layer and surrounds sidewalls of the trench, wherein the barrier region prevents a dopant used for forming the doped region from reaching the epitaxial layer under the barrier region. The trench is filled with a dielectric material. A pair of polysilicon gates is formed on the epitaxial layer and on both sides of the trench.Type: GrantFiled: October 26, 2012Date of Patent: June 2, 2015Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Tsung-Hsiung Lee, Shang-Hui Tu, Gene Sheu, Neelam Agarwal, Karuna Nidhi, Chia-Hao Lee, Rudy Octavius Sihombing
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Patent number: 8912599Abstract: A semiconductor device is provided. The semiconductor device includes a drain region, a source region, a channel region and a hybrid doped region. The drain region of a first conductivity type is located in a substrate. The source region of the first conductivity type is located in the substrate and surrounding the drain region. The channel region is located in the substrate between the source region and the drain region. The hybrid doped region includes a top doped region and a compensation doped region. The top doped region is of a second conductivity type, having a doping concentration decreased from a region near the channel region to a region near the drain region, and located in the substrate between the channel region and the drain region. The compensation doped region of the first conductivity type is located in the top doped region to compensate the top doped region.Type: GrantFiled: October 8, 2013Date of Patent: December 16, 2014Assignee: Nuvoton Technology CorporationInventors: Po-An Chen, Gene Sheu, Shao-Ming Yang, MD Imran Siddiqui
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Publication number: 20140117436Abstract: A method for fabricating a semiconductor device is provided. An epitaxial layer is grown on a substrate, wherein the epitaxial layer and the substrate have a first conductivity type. A trench is formed in the epitaxial layer. A barrier region is formed at a bottom of the trench. A doped region of a second conductivity type is formed in the epitaxial layer and surrounds sidewalls of the trench, wherein the barrier region prevents a dopant used for forming the doped region from reaching the epitaxial layer under the barrier region. The trench is filled with a dielectric material. A pair of polysilicon gates is formed on the epitaxial layer and on both sides of the trench.Type: ApplicationFiled: October 26, 2012Publication date: May 1, 2014Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Tsung-Hsiung LEE, Shang-Hui TU, Gene SHEU, Neelam AGARWAL, Karuna NIDHI, Chia-Hao LEE, Rudy Octavius SIHOMBING
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Publication number: 20140061788Abstract: A semiconductor device is provided. The semiconductor device includes a drain region, a source region, a channel region and a hybrid doped region. The drain region of a first conductivity type is located in a substrate. The source region of the first conductivity type is located in the substrate and surrounding the drain region. The channel region is located in the substrate between the source region and the drain region. The hybrid doped region includes a top doped region and a compensation doped region. The top doped region is of a second conductivity type, having a doping concentration decreased from a region near the channel region to a region near the drain region, and located in the substrate between the channel region and the drain region. The compensation doped region of the first conductivity type is located in the top doped region to compensate the top doped region.Type: ApplicationFiled: October 8, 2013Publication date: March 6, 2014Applicant: Nuvoton Technology CorporationInventors: Po-An Chen, Gene Sheu, Shao-Ming Yang, MD Imran Siddiqui
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Patent number: 8592901Abstract: A metal oxide semiconductor field transistor including a gate electrode, a gate dielectric layer, a source region, a drain region, and a top doped region are provided. The drain region of a first conductivity type is located in a substrate. The source region of the first conductivity type is located in the substrate and surrounded the drain region. The gate electrode is located above the substrate between the source region and the drain region. The gate dielectric layer is located between the gate electrode and the substrate. The top doped region of a second conductivity type is located in the substrate between the gate electrode and the drain region. The top doped region includes at least three regions. Each of the three regions has a dopant concentration gradient and a concentration gradually decreased from a region adjacent the gate electrode to a region adjacent the drain region.Type: GrantFiled: November 29, 2012Date of Patent: November 26, 2013Assignee: Nuvoton Technology CorporationInventors: Gene Sheu, MD Imran Siddiqui, Abijith Prakash, Shao-Ming Yang, Jung-Ruey Tsai
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Patent number: 8252652Abstract: A semiconductor structure is provided. A second conductivity type well region is formed on a first conductivity type substrate. A second conductivity type diffused source and second conductivity type diffused drain are formed on the first conductivity type substrate. A gate structure is formed on the second conductivity type well region between the second conductivity type diffused source and the second conductivity type diffused drain. First conductivity type buried rings are arranged in a horizontal direction, and formed in the second conductivity type well region, and divide the second conductivity type well region into an upper drift region and a lower drift region.Type: GrantFiled: March 29, 2010Date of Patent: August 28, 2012Assignee: Vanguard International Semiconductor CorporationInventors: Yih-Jau Chang, Shang-Hui Tu, Gene Sheu, Yi-Fong Chang, Nithin Devarajulu Palavalli
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Patent number: 8154078Abstract: A semiconductor structure is provided. A second conductivity type well region is disposed on a first conductivity type substrate. A gate structure comprising a first sidewall and second sidewall is provided. The first sidewall is disposed on the second conductivity type well region. A second conductivity type diffused source is disposed on the first conductivity type substrate outside of the second sidewall. A second conductivity type diffused drain is disposed on the second conductivity type well region outside of the first sidewall. First conductivity type buried rings are arranged in a horizontal direction, separated from each other, and formed in the second conductivity type well region. Doped profiles of the first conductivity type buried rings gradually become smaller in a direction from the second conductivity type diffused source to the second conductivity type diffused drain.Type: GrantFiled: February 17, 2010Date of Patent: April 10, 2012Assignee: Vanguard International Semiconductor CorporationInventors: Yih-Jau Chang, Shang-Hui Tu, Gene Sheu
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Publication number: 20110233672Abstract: A semiconductor structure is provided. A second conductivity type well region is formed on a first conductivity type substrate. A second conductivity type diffused source and second conductivity type diffused drain are formed on the first conductivity type substrate. A gate structure is formed on the second conductivity type well region between the second conductivity type diffused source and the second conductivity type diffused drain. First conductivity type buried rings are arranged in a horizontal direction, and formed in the second conductivity type well region, and divide the second conductivity type well region into an upper drift region and a lower drift region.Type: ApplicationFiled: March 29, 2010Publication date: September 29, 2011Inventors: Yih-Jau CHANG, Shang-Hui Tu, Gene Sheu, Yi-Fong Chang, Nithin Devarajulu Palavalli
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Publication number: 20110198692Abstract: A semiconductor structure is provided. A second conductivity type well region is disposed on a first conductivity type substrate. A gate structure comprising a first sidewall and second sidewall is provided. The first sidewall is disposed on the second conductivity type well region. A second conductivity type diffused source is disposed on the first conductivity type substrate outside of the second sidewall. A second conductivity type diffused drain is disposed on the second conductivity type well region outside of the first sidewall. First conductivity type buried rings are arranged in a horizontal direction, separated from each other, and formed in the second conductivity type well region. Doped profiles of the first conductivity type buried rings gradually become smaller in a direction from the second conductivity type diffused source to the second conductivity type diffused drain.Type: ApplicationFiled: February 17, 2010Publication date: August 18, 2011Inventors: Yih-Jau CHANG, Shang-Hui TU, Gene SHEU