Abstract: A method, system, and program for selectively testing output signals of an integrated circuit. The system comprising a mask generation file specifying output signals and test cycles and a verification module to check simulation output data and generate test pattern data. The verification module further comprising an extractor routine which receives the mask generation file and processes the simulation output data such that the test pattern data is coded to mask the specified output signals at the specified test cycles. The verification module further comprising margin analysis for determining if margin times of the coded test patterns fall below a minimum margin time setting.

Abstract: A system comprises translation software to convert non-tester-compatible simulation results into tester-compatible test patterns in a ATE system. An intermediate output of the system includes tester-compatible input stimulus for use in re-simulating a circuit design. The resulting simulation output data is tester-compatible, by definition, and can be used to generate tester-compatible test patterns that correspond to a verified simulation of the circuit design. Partnered time sets and signal state data are used in translation between tester-compatible and non-tester-compatible timings.

Abstract: A method for simulating an integrated circuit design that automatically generates an interface between a test bench and a device design for simulation. The method determines that the signal format and timing information of the test bench conforms to the constraints of some target ATE. If the information conforms, an array of buffers is created to provide the interface. Each of the buffers are defined according to the signal timing information. The interface is then incorporated into a test bench stimuli generator and the design is simulated. In this manner, the method allows for the generation of a simulation that can be then reproduced on any target ATE.