Patents by Inventor Geng-Yen Lee
Geng-Yen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10283631Abstract: In one aspect of the present disclosure, a semiconductor device includes a channel layer, an AlxIn1-xN layer on the channel layer with a thickness of t1, and a reverse polarization layer on the AlxIn1-xN layer with a thickness of t2. The thickness is 0.5×t1?t2?3×t1. In another aspect of the present disclosure, a method of manufacturing a semiconductor device is provided. The method including: forming a channel layer on a substrate; forming an AlxIn1-xN layer on the channel layer with a thickness of t1; and forming a reverse polarization layer on the AlxIn1-xN layer with a thickness of t2. The thickness is 0.5×t1?t2?3×t1.Type: GrantFiled: May 12, 2016Date of Patent: May 7, 2019Assignees: DELTA ELECTRONICS, INC., NATIONAL CENTRAL UNIVERSITYInventors: Chun-Chieh Yang, Jen-Inn Chyi, Geng-Yen Lee
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Patent number: 9640672Abstract: A diode device including a III-N compound layer is provided. The III-N compound layer has a channel region therein. A cathode region is located on the III-N compound layer. A first anode region is located on the III-N compound layer and extends into the III-N compound layer. The bottom of the first anode region is under the channel region. A second anode region is located on the III-N compound layer between the cathode region and the first anode region, and extends into the III-N compound material layer. The second anode region includes a high-energy barrier region. The high-energy barrier region adjoins a sidewall of the first anode region. A method for manufacturing a diode device is also provided.Type: GrantFiled: February 10, 2016Date of Patent: May 2, 2017Assignees: National Central University, Delta Electronics, Inc.Inventors: Jen-Inn Chyi, Bo-Shiang Wang, Chun-Chieh Yang, Geng-Yen Lee
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Publication number: 20160336436Abstract: In one aspect of the present disclosure, a semiconductor device includes a channel layer, an AlxIn1-xN layer on the channel layer with a thickness of t1, and a reverse polarization layer on the AlxIn1-xN layer with a thickness of t2. The thickness is 0.5×t1?t2?3×t1. In another aspect of the present disclosure, a method of manufacturing a semiconductor device is provided. The method including: forming a channel layer on a substrate; forming an AlxIn1-xN layer on the channel layer with a thickness of t1; and forming a reverse polarization layer on the AlxIn1-xN layer with a thickness of t2. The thickness is 0.5×t1?t2?3×t1.Type: ApplicationFiled: May 12, 2016Publication date: November 17, 2016Inventors: Chun-Chieh YANG, Jen-Inn CHYI, Geng-Yen LEE
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Publication number: 20160315204Abstract: A diode device including a III-N compound layer is provided. The III-N compound layer has a channel region therein. A cathode region is located on the III-N compound layer. A first anode region is located on the III-N compound layer and extends into the III-N compound layer. The bottom of the first anode region is under the channel region. A second anode region is located on the III-N compound layer between the cathode region and the first anode region, and extends into the III-N compound material layer. The second anode region includes a high-energy barrier region. The high-energy barrier region adjoins a sidewall of the first anode region. A method for manufacturing a diode device is also provided.Type: ApplicationFiled: February 10, 2016Publication date: October 27, 2016Inventors: JEN-INN CHYI, BO-SHIANG WANG, CHUN-CHIEH YANG, GENG-YEN LEE
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Patent number: 9093510Abstract: A field effect transistor device is provided by the invention. The field effect transistor device includes: a substrate; a buffer layer, a channel layer, and a first barrier layer sequentially disposed on the substrate; a two-dimensional electron gas controlling layer disposed on the first barrier layer; a second barrier layer disposed on the two-dimensional electron gas controlling layer, wherein the second barrier layer has a recess passing through the second barrier layer; and a gate electrode filled into the recess and separated from the second barrier layer and the two-dimensional electron gas controlling layer by an insulating layer.Type: GrantFiled: August 8, 2013Date of Patent: July 28, 2015Assignees: NATIONAL CENTRAL UNIVERSITY, DELTA ELECTRONICS, INC.Inventors: Jen-Inn Chyi, Hui-Ling Lin, Geng-Yen Lee, Shih-Peng Chen
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Patent number: 9070708Abstract: A semiconductor device including a substrate, a heterojunction body, a passivation layer, a source contact, a drain contact, and a gate contact. The heterojunction body disposed on or above the substrate includes a first semiconductor layer, a mask layer, a regrowth layer, and a second semiconductor layer. The first semiconductor layer is disposed on or above the substrate. The mask layer is disposed on or above a portion of the first semiconductor layer. The regrowth layer disposed on the first semiconductor layer and adjacent to the mask layer includes a main portion and at least one inclined portion. The second semiconductor layer is disposed on the mask layer and the regrowth layer. The passivation layer is disposed on the second semiconductor layer. The gate contact is disposed on the passivation layer, between the source contact and the drain contact, and at least above the inclined portion of the regrowth layer.Type: GrantFiled: January 27, 2014Date of Patent: June 30, 2015Assignees: NATIONAL CENTRAL UNIVERSITY, DELTA ELECTRONICS, INC.Inventors: Jen-Inn Chyi, Geng-Yen Lee, Wei-Kai Shen, Ching-Chuan Shiue, Tai-Kang Shing
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Publication number: 20140264450Abstract: A semiconductor device including a substrate, a heterojunction body, a passivation layer, a source contact, a drain contact, and a gate contact. The heterojunction body disposed on or above the substrate includes a first semiconductor layer, a mask layer, a regrowth layer, and a second semiconductor layer. The first semiconductor layer is disposed on or above the substrate. The mask layer is disposed on or above a portion of the first semiconductor layer. The regrowth layer disposed on the first semiconductor layer and adjacent to the mask layer includes a main portion and at least one inclined portion. The second semiconductor layer is disposed on the mask layer and the regrowth layer. The passivation layer is disposed on the second semiconductor layer. The gate contact is disposed on the passivation layer, between the source contact and the drain contact, and at least above the inclined portion of the regrowth layer.Type: ApplicationFiled: January 27, 2014Publication date: September 18, 2014Applicants: DELTA ELECTRONICS, INC., National Central UniversityInventors: Jen-Inn CHYI, Geng-Yen LEE, Wei-Kai SHEN, Ching-Chuan SHIUE, Tai-Kang SHING
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Patent number: 8679881Abstract: A growth method for reducing defect density of GaN includes steps of: sequentially forming a buffer growth layer, a stress release layer and a first nanometer cover layer on a substrate, wherein the first nanometer cover layer has multiple openings interconnected with the stress release layer; growing a first island in each of the openings; growing a first buffer layer and a second nanometer cover layer on the first island; and growing a second island to form a dislocated island structure. Thus, through the first nanometer cover layer and the second nanometer cover layer, multiple dislocated island structures can be directly formed to reduce manufacturing complexity as well as increase yield rate by decreasing manufacturing environment variation. Further, the epitaxial lateral over growth (ELOG) approach also effectively enhances characteristics of GaN optoelectronic semiconductor elements.Type: GrantFiled: July 3, 2013Date of Patent: March 25, 2014Assignee: Tekcore Co., Ltd.Inventors: Jen-Inn Chyi, Lung-Chieh Cheng, Hsueh-Hsing Liu, Geng-Yen Lee
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Publication number: 20140042455Abstract: A field effect transistor device is provided by the invention. The field effect transistor device includes: a substrate; a buffer layer, a channel layer, and a first barrier layer sequentially disposed on the substrate; a two-dimensional electron gas controlling layer disposed on the first barrier layer; a second barrier layer disposed on the two-dimensional electron gas controlling layer, wherein the second barrier layer has a recess passing through the second barrier layer; and a gate electrode filled into the recess and separated from the second barrier layer and the two-dimensional electron gas controlling layer by an insulating layer.Type: ApplicationFiled: August 8, 2013Publication date: February 13, 2014Applicants: Delta Electronics, Inc., National Central UniversityInventors: Jen-Inn CHYI, Hui-Ling LIN, Geng-Yen LEE, Shih-Peng CHEN
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Patent number: 8586995Abstract: A semiconductor element having a high breakdown voltage includes a substrate, a buffer layer, a semiconductor composite layer and a bias electrode. The buffer layer disposed on the substrate includes a high edge dislocation defect density area. The semiconductor composite layer disposed on the buffer layer includes a second high edge dislocation defect density area formed due to the first high edge dislocation defect density area. The bias electrode is disposed on the semiconductor composite layer. A virtual gate effect of defect energy level capturing electrons is generated due to the first and second high edge dislocation defect density areas, such that an extended depletion region expanded from the bias electrode is formed at the semiconductor composite layer. When the bias electrode receives a reverse bias, the extended depletion region reduces a leakage current and increases the breakdown voltage of the semiconductor element.Type: GrantFiled: August 9, 2012Date of Patent: November 19, 2013Assignee: National Central UniversityInventors: Jen-Inn Chyi, Geng-Yen Lee, Hsueh-Hsing Liu
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Publication number: 20130240895Abstract: A semiconductor element having a high breakdown voltage includes a substrate, a buffer layer, a semiconductor composite layer and a bias electrode. The buffer layer disposed on the substrate includes a high edge dislocation defect density area. The semiconductor composite layer disposed on the buffer layer includes a second high edge dislocation defect density area formed due to the first high edge dislocation defect density area. The bias electrode is disposed on the semiconductor composite layer. A virtual gate effect of defect energy level capturing electrons is generated due to the first and second high edge dislocation defect density areas, such that an extended depletion region expanded from the bias electrode is formed at the semiconductor composite layer. When the bias electrode receives a reverse bias, the extended depletion region reduces a leakage current and increases the breakdown voltage of the semiconductor element.Type: ApplicationFiled: August 9, 2012Publication date: September 19, 2013Inventors: Jen-Inn CHYI, Geng-Yen Lee, Hsueh-Hsing Liu
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Patent number: 8426226Abstract: A method for fabricating an integrated AC LED module comprises steps: forming a junction layer on a substrate, and defining a first growth area and a second growth area on the junction layer; respectively growing a Schottky diode and a LED on the first growth area and the second growth area; forming a passivation layer and a metallic layer on the Schottky diode, the LED and the substrate. Thereby, the Schottky diode is electrically connected with the LED via the metallic layer. Thus is promoted the reliability of electric connection of diodes, reduced the layout area of the module, and decreased the fabrication cost.Type: GrantFiled: January 3, 2012Date of Patent: April 23, 2013Assignee: National Central UniversityInventors: Jen-Inn Chyi, Geng-Yen Lee, Wei-Sheng Lin
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Publication number: 20130034919Abstract: A method for fabricating an integrated AC LED module comprises steps: forming a junction layer on a substrate, and defining a first growth area and a second growth area on the junction layer; respectively growing a Schottky diode and a LED on the first growth area and the second growth area; forming a passivation layer and a metallic layer on the Schottky diode, the LED and the substrate. Thereby, the Schottky diode is electrically connected with the LED via the metallic layer. Thus is promoted the reliability of electric connection of diodes, reduced the layout area of the module, and decreased the fabrication cost.Type: ApplicationFiled: January 3, 2012Publication date: February 7, 2013Inventors: Jen-Inn CHYI, Geng-Yen Lee, Wei-Sheng Lin