Abstract: Before a semiconductor die of a brittle III-V compound semiconductor is encapsulated with a molding compound during package fabrication, side surfaces of the semiconductor die are treated to avoid or prevent surface imperfections from propagating and fracturing the crystal structure of the substrate of the III-V compound semiconductor under the stresses applied as the molding compound solidifies. Surfaces are treated to form a passivation layer, which may be a passivated layer of the substrate or a passivation material on the substrate. In a passivated layer, imperfections of an external layer are transformed to be less susceptible to fracture. Passivation material, such as a poly-crystalline layer on the substrate surface, diffuses stresses that are applied by the molding compound. Semiconductor dies in flip-chip and wire-bond chip packages with treated side surfaces as disclosed have a reduced incidence of failure caused by die fracturing.

Abstract: Aspects generally relate to a heterojunction bipolar transistor (HBT), and method of manufacturing the same. The HBT including an emitter a first, a first side of a base coupled to a second side of the emitter opposite the first side of the emitter. A collector coupled to the base on a second side of the base opposite the emitter, wherein an area of a junction between the base and the collector is less than or equal to an area of a junction between the base and the emitter. A dielectric coupled to the collector. A first conductive base contact coupled to the base and adjacent to the collector and extending over a base-collector junction, the conductive base contact operative as a field plate.

Abstract: A distributed feedback (DFB) laser that includes a substrate comprising a first surface and a second surface, wherein the substrate comprises silicon; a plurality of shallow trench isolations (STIs) located over the second surface of the substrate; a grating region located over the plurality of STIs and the substrate, wherein the grating region comprises a III-V semiconductor material; a non-intentional doping (NID) region located over the grating region; and a contact region located over the NID region.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device implemented with multiple channels in a gate-all-around (GAA) high-electron-mobility transistor (HEMT) and techniques for fabricating such a device. One example semiconductor device generally includes a substrate; a first gate layer disposed above the substrate; a first barrier layer disposed above the first gate layer; a first channel region disposed above the first barrier layer; a second barrier layer disposed above the first channel region; a second gate layer disposed above the second barrier layer; a third barrier layer disposed above the second gate layer; a second channel region disposed above the third barrier layer; a fourth barrier layer disposed above the second channel region; a source region; and a drain region.

Abstract: Certain aspects of the present disclosure generally relate to a vertically stacked multilayer resistive random access memory (RRAM) and methods for fabricating such an RRAM. The vertically stacked multilayer RRAM generally includes a planar substrate layer and a plurality of metal-insulator-metal (MIM) stacks, each MIM stack structure of the plurality of MIM stacks comprising a plurality of MIM structures extending orthogonally above the planar substrate.

Abstract: Before a semiconductor die of a brittle compound semiconductor is encapsulated with a molding compound during package fabrication, side surfaces of the semiconductor die are treated to avoid or prevent surface imperfections from propagating and fracturing the crystal structure of the substrate of the III-V compound semiconductor under the stresses applied as the molding compound solidifies. Surfaces are treated to form a passivation layer, which may be a passivated layer of the substrate or a passivation material on the substrate. In a passivated layer, imperfections of an external layer are transformed to be less susceptible to fracture. Passivation material, such as a poly-crystalline layer on the substrate surface, diffuses stresses that are applied by the molding compound. Semiconductor dies in flip-chip and wire-bond chip packages with treated side surfaces as disclosed have a reduced incidence of failure caused by die fracturing.

Abstract: A distributed feedback (DFB) laser that includes a substrate comprising a first surface and a second surface, wherein the substrate comprises silicon; a plurality of shallow trench isolations (STIs) located over the second surface of the substrate; a grating region located over the plurality of STIs and the substrate, wherein the grating region comprises a III-V semiconductor material; a non-intentional doping (NID) region located over the grating region; and a contact region located over the NID region.

Abstract: Certain aspects of the present disclosure generally relate to a vertically stacked multilayer resistive random access memory (RRAM) and methods for fabricating such an RRAM. The vertically stacked multilayer RRAM generally includes a planar substrate layer and a plurality of metal-insulator-metal (MIM) stacks, each MIM stack structure of the plurality of MIM stacks comprising a plurality of MIM structures extending orthogonally above the planar substrate.

Abstract: Certain aspects of the present disclosure provide a high electron mobility transistor (HEMT). The HEMT generally includes a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer disposed above the GaN layer. The HEMT also includes a source electrode, a gate electrode, and a drain electrode disposed above the AlGaN layer. The HEMT further includes n-doped protuberance(s) disposed above the AlGaN layer and disposed between at least one of: the gate electrode and the drain electrode; or the source electrode and the gate electrode. Each of the n-doped protuberances is separated from the gate electrode, the drain electrode, and the source electrode.

Abstract: Certain aspects of the present disclosure generally relate to a vertical resistive random access memory (RRAM). The vertical RRAM generally includes a planar substrate layer and a plurality of fin-like metal-insulator-metal (MIM) structures extending orthogonally above the substrate layer.

Abstract: Certain aspects of the present disclosure are directed to a resistive random access memory (RRAM). The RRAM generally includes a substrate, an insulator region disposed above the substrate, and a gate region disposed adjacent to at least one lateral surface of the insulator region. The RRAM may also include a first non-insulative region disposed adjacent to a lower surface of the insulator region, and a second non-insulative region disposed adjacent to an upper surface of the insulator region.

Abstract: Aspects generally relate to a P-N junction varactor that can be integrated with high electron mobility transistor (HEMT) in a single device or die. The varactor and HEMT are fabricated with the same materials forming various layers of the varactor and HEMT. Using the same material stack-up to form the varactor and HEMT can reduce the number of processing steps during the fabrication of the integrated varactor and HEMT device. The integrated varactor and HEMT device may be used for RF circuits, such as radio frequency front end (RFFE) devices for use in 5G.

Abstract: Aspects generally relate to a P-N junction varactor that can be integrated with high electron mobility transistor (HEMT) in a single device or die. The varactor and HEMT are fabricated with the same materials forming various layers of the varactor and HEMT. Using the same material stack-up to form the varactor and HEMT can reduce the number of processing steps during the fabrication of the integrated varactor and HEMT device. The integrated varactor and HEMT device may be used for RF circuits, such as radio frequency front end (RFFE) devices for use in 5G.

Abstract: Aspects generally relate to a P?N junction varactor that can be integrated with high electron mobility transistor (HEMT) in a single device or die. The varactor and HEMT are fabricated with different materials forming various layers of the varactor and HEMT. Using different material stack-up to form the varactor and HEMT allows characteristics of the varactor and HEMT to be varied for improved performance in different operating scenarios. The integrated varactor and HEMT device may be used for RF circuits, such as radio frequency front end (RFFE) devices for use in 5G.

Abstract: Low resistance source/drain regions in III-V transistors are disclosed. More particularly, a source and a drain are formed from heavily doped III-V materials that have lower resistances than a barrier layer and/or a cap layer under the drain. In an exemplary aspect, the barrier and cap layers are formed over a mobility channel layer and then etched to form source and drain recesses. A source and a drain are then epitaxially grown in the recesses. The source and the drain may include one or more layers, with the top layer having the lowest bandgap, thus helping to lower contact resistance. By lowering the resistance of the source and the drain, the overall resistance of the transistor may be lowered to allow for operation at higher frequencies.

Abstract: Certain aspects of the present disclosure are directed to a memory device and techniques for fabricating a memory device. One example memory device generally includes a substrate layer, a channel layer disposed above and having a longitudinal axis perpendicular to a horizontal plane of the substrate layer, and a plurality of charge trap (CT) regions disposed adjacent to the channel layer, the plurality of CT regions being separate regions that are electrically isolated from one another. In certain aspects, the memory device also includes a plurality of gate layers, each gate layer of the plurality of gate layers being disposed adjacent to one of the plurality of CT regions.

Abstract: A wafer carrier comprising a board, a frame and at least one bolt and nut combination. The board includes at least one vacuum cavity and at least one securing cavity. The frame is coupled to the board. The at least one bolt and nut combination is configured to secure the frame to the board. The board may include one or more metal layers. The frame may include a plurality of scattered frames or a disc shaped frame. The frame may comprise a cavity for the bolt travels through the frame. The wafer carrier may include a wafer located over the board, wherein the wafer is located between the board and the frame.

Abstract: Aspects generally relate to a heterojunction bipolar transistor (HBT), and method of manufacturing the same. The HBT including an emitter a first, a first side of a base coupled to a second side of the emitter opposite the first side of the emitter. A collector coupled to the base on a second side of the base opposite the emitter, wherein an area of a junction between the base and the collector is less than or equal to an area of a junction between the base and the emitter. A dielectric coupled to the collector. A first conductive base contact coupled to the base and adjacent to the collector and extending over a base-collector junction, the conductive base contact operative as a field plate.

Abstract: A compound semiconductor field effect transistor may include a channel layer. The compound semiconductor transistor may also include a multi-layer epitaxial barrier layer on the channel layer. The channel layer may be on a doped buffer layer or on a first un-doped buffer layer. The compound semiconductor field effect transistor may further include a gate. The gate may be on a first tier of the multi-layer epitaxial barrier layer, and through a space between portions of a second tier of the multi-layer epitaxial barrier layer.

Abstract: Power amplifiers in radio frequency circuits are typically implemented as heterojunction bipolar transistors. In applications such as in 5G systems, the circuits are expected to operate at very high speeds, e.g., up to 100 GHz. Also, a certain amount of output power should be maintained for stable operation. To achieve both high power and high speed, it is proposed to incorporate field plates in the heterojunction bipolar transistors to reduce electric field in the collector. This allows the breakdown voltage of the transistor to be high, which aids in power output. At the same time, the collector can be relatively thin, which aids in operation speed.