Patents by Inventor Genis Chapinal

Genis Chapinal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220264042
    Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to row control circuitry and column readout circuitry. An image pixel in the array may include a charge integration portion having a photodiode, a floating diffusion region, and a capacitor coupled to the floating diffusion region and may include a voltage-domain sampling portion having three capacitors. High light and low light image level and reset level signals may be sampled and stored at the voltage-domain sampling portion before being readout to the column readout circuitry during a readout operation. The high light reset level signal may be sampled and stored during the readout operation.
    Type: Application
    Filed: February 3, 2022
    Publication date: August 18, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Manuel H. INNOCENT, Tomas GEURTS, Genis CHAPINAL GOMEZ, Tze Ching FUNG, Bartosz Piotr BANACHOWICZ
  • Patent number: 11165977
    Abstract: An imaging system may include an image sensor having an image sensor. The image sensor may include an image sensor pixel array coupled to row control circuitry and column readout circuitry. The image sensor pixel array may include a plurality of image sensor pixels. Each image sensor pixel may include a photosensitive element configured to generate charge in response to incident light, a first charge storage structure configured to accumulate an overflow portion of the generated charge for a low gain signal and a second charge storage structure configured to store a remaining portion of the generated charge for a high gain signal. Each image sensor pixel may also include a dedicated overflow charge storage structure interposed between the first charge storage structure and a floating diffusion region.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: November 2, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Tomas Geurts, Manuel H. Innocent, Robert Michael Guidash, Genis Chapinal
  • Publication number: 20210029312
    Abstract: An imaging system may include an image sensor having an image sensor. The image sensor may include an image sensor pixel array coupled to row control circuitry and column readout circuitry. The image sensor pixel array may include a plurality of image sensor pixels. Each image sensor pixel may include a photosensitive element configured to generate charge in response to incident light, a first charge storage structure configured to accumulate an overflow portion of the generated charge for a low gain signal and a second charge storage structure configured to store a remaining portion of the generated charge for a high gain signal. Each image sensor pixel may also include a dedicated overflow charge storage structure interposed between the first charge storage structure and a floating diffusion region.
    Type: Application
    Filed: April 28, 2020
    Publication date: January 28, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Tomas GEURTS, Manuel H. INNOCENT, Robert Michael GUIDASH, Genis CHAPINAL
  • Patent number: 8723606
    Abstract: In accordance with an embodiment, a gain enhancement circuit includes an amplifier having an input terminal, a transistor coupled to the input terminal and a capacitance dynamically coupled to another input terminal of the amplifier by a switch, wherein the capacitance is a parasitic element of the transistor.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: May 13, 2014
    Inventors: Yannick De Wit, Ishwar Chandra Mudegowdar, Genis Chapinal
  • Publication number: 20120206202
    Abstract: In accordance with an embodiment, a gain enhancement circuit includes an amplifier having an input terminal, a transistor coupled to the input terminal and a capacitance dynamically coupled to another input terminal of the amplifier by a switch, wherein the capacitance is a parasitic element of the transistor.
    Type: Application
    Filed: February 14, 2012
    Publication date: August 16, 2012
    Inventors: Yannick De Wit, Ishwar Chandra Mudegowdar, Genis Chapinal