Patents by Inventor Gennette Delaine Gill

Gennette Delaine Gill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9537679
    Abstract: A dynamically reconfigurable asynchronous arbitration node for use in an adaptive asynchronous interconnection network is provided. The arbitration node includes a circuit, an output channel and two input channels—a first input channel and a second input channel. The circuit supports a default-arbitration mode and a biased-input mode. The circuit is configured to generate data for the output channel by mediating between input traffic including data received at the first and second input channels, if the arbitration node is operating in the default-arbitration mode, or by providing a direct path to the output channel for one of the first input channel and the second input channel that is biased, if the arbitration node is operating in the biased-input mode. The circuit is further configured to monitor the input traffic and implement a mode change based on a history of the observed input traffic in accordance with a mode-change policy.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: January 3, 2017
    Assignee: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
    Inventors: Steven M. Nowick, Gennette Delaine Gill, Sumedh S. Attarde
  • Patent number: 8872544
    Abstract: Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits are disclosed. According to one aspect, the subject matter described herein includes a configurable system for constructing asynchronous application specific integrated data pipeline circuits. The system includes multiple modular circuit stages that are connectable with each other using transitional signaling and with other circuit elements to form multi-stage asynchronous application-specific integrated data pipeline circuits for asynchronously passing data through a series of stages based on a behavior implemented by each stage. The modular circuit stages each include sets of logic gates connected to each other for implementing the behaviors, the behaviors including at least one of conditional split, conditional select, conditional join, merge without arbitration, and stage arbitration.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: October 28, 2014
    Assignee: The University of North Carolina at Chapel Hill
    Inventors: Gennette Delaine Gill, Montek Singh
  • Publication number: 20140247069
    Abstract: Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits are disclosed. According to one aspect, the subject matter described herein includes a configurable system for constructing asynchronous application specific integrated data pipeline circuits. The system includes multiple modular circuit stages that are connectable with each other using transitional signaling and with other circuit elements to form multi-stage asynchronous application-specific integrated data pipeline circuits for asynchronously passing data through a series of stages based on a behavior implemented by each stage. The modular circuit stages each include sets of logic gates connected to each other for implementing the behaviors, the behaviors including at least one of conditional split, conditional select, conditional join, merge without arbitration, and stage arbitration.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 4, 2014
    Applicant: THE UNIVERSITY OF NORTH CAROLINA AT CHAPEL HILL
    Inventors: Gennette Delaine Gill, Montek Singh
  • Publication number: 20140241443
    Abstract: A dynamically reconfigurable asynchronous arbitration node for use in an adaptive asynchronous interconnection network is provided. The arbitration node includes a circuit, an output channel and two input channels—a first input channel and a second input channel. The circuit supports a default-arbitration mode and a biased-input mode. The circuit is configured to generate data for the output channel by mediating between input traffic including data received at the first and second input channels, if the arbitration node is operating in the default-arbitration mode, or by providing a direct path to the output channel for one of the first input channel and the second input channel that is biased, if the arbitration node is operating in the biased-input mode. The circuit is further configured to monitor the input traffic and implement a mode change based on a history of the observed input traffic in accordance with a mode-change policy.
    Type: Application
    Filed: March 14, 2012
    Publication date: August 28, 2014
    Inventors: Steven M. Nowick, Gennette Delaine Gill, Sumedh S. Attarde
  • Patent number: 8669779
    Abstract: Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits are disclosed. According to one aspect, the subject matter described herein includes a configurable system for constructing asynchronous application specific integrated data pipeline circuits. The system includes multiple modular circuit stages that are connectable with each other using transitional signaling and with other circuit elements to form multi-stage asynchronous application-specific integrated data pipeline circuits for asynchronously passing data through a series of stages based on a behavior implemented by each stage. The modular circuit stages each include sets of logic gates connected to each other for implementing the behaviors, the behaviors including at least one of conditional split, conditional select, conditional join, merge without arbitration, and stage arbitration.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: March 11, 2014
    Assignee: The University of North Carolina at Chapel Hill
    Inventors: Gennette Delaine Gill, Montek Singh
  • Publication number: 20110169525
    Abstract: Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits are disclosed. According to one aspect, the subject matter described herein includes a configurable system for constructing asynchronous application specific integrated data pipeline circuits. The system includes multiple modular circuit stages that are connectable with each other using transitional signaling and with other circuit elements to form multi-stage asynchronous application-specific integrated data pipeline circuits for asynchronously passing data through a series of stages based on a behavior implemented by each stage. The modular circuit stages each include sets of logic gates connected to each other for implementing the behaviors, the behaviors including at least one of conditional split, conditional select, conditional join, merge without arbitration, and stage arbitration.
    Type: Application
    Filed: June 29, 2009
    Publication date: July 14, 2011
    Inventors: Gennette Delaine Gill, Montek Singh