Abstract: A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row of the array is formed on the substrate and coupled to MC current paths for the corresponding row. Bit lines corresponding to respective columns of the array are formed on the substrate and can be coupled to a modulation doped QW interface of the MC thyristors for the corresponding column. Circuitry is configured to apply an electrical signal to the word line(s) in order to generate current that programs phase change material of the MC load elements into one of a high or low resistive state according to state of the current path of the MCs for non-volatile backup purposes.

Abstract: A semiconductor device is provided that includes an array of imaging cells realized from a plurality of layers formed on a substrate, wherein the plurality of layers includes at least one modulation doped quantum well structure spaced from at least one quantum dot structure. Each respective imaging cell includes an imaging region spaced from a corresponding charge storage region. The at least one quantum dot structure of the imaging region generates photocurrent arising from absorption of incident electromagnetic radiation. The at least one modulation doped quantum well structure defines a buried channel for lateral transfer of the photocurrent for charge accumulation in the charge storage region and output therefrom. The at least one modulation doped quantum well structure and the at least one quantum dot structure of each imaging cell can be disposed within a resonant cavity that receives the incident electromagnetic radiation or below a structured metal film having a periodic array of holes.

Abstract: A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row of the array is formed on the substrate and coupled to MC current paths for the corresponding row. Bit lines corresponding to respective columns of the array are formed on the substrate and can be coupled to a modulation doped QW interface of the MC thyristors for the corresponding column. Circuitry is configured to apply an electrical signal to the word line(s) in order to generate current that programs phase change material of the MC load elements into one of a high or low resistive state according to state of the current path of the MCs for non-volatile backup purposes.

Abstract: A monolithic semiconductor device that includes a waveguide structure optically coupled to an optical resonator. The optical resonator is adapted to process light at a predetermined wavelength. The optical resonator includes a closed loop waveguide having a plurality of straight sections that are optically coupled together by bend sections.

Abstract: A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row of the array is formed on the substrate and coupled to MC current paths for the corresponding row. Bit lines corresponding to respective columns of the array are formed on the substrate and can be coupled to a modulation doped QW interface of the MC thyristors for the corresponding column. Circuitry is configured to apply an electrical signal to the word line(s) in order to generate current that programs phase change material of the MC load elements into one of a high or low resistive state according to state of the current path of the MCs for non-volatile backup purposes.

Abstract: A semiconductor device includes a substrate supporting a plurality of layers that include at least one modulation doped quantum well (QW) structure offset from a quantum dot in quantum well (QD-in-QW) structure. The modulation doped QW structure includes a charge sheet spaced from at least one QW by a spacer layer. The QD-in-QW structure has QDs embedded in one or more QWs. The QD-in-QW structure can include at least one template/emission substructure pair separated by a barrier layer, the template substructure having smaller size QDs than the emission substructure. A plurality of QD-in-QW structures can be provided to support the processing (emission, absorption, amplification) of electromagnetic radiation of different characteristic wavelengths (such as optical wavelengths in range from 1300 nm to 1550 nm).

Abstract: An array of thyristor detector devices is provided having an epitaxial growth structure with complementary types of modulation doped quantum well interfaces located between a P+ layer and an N+ layer. The thyristor detector devices operate over successive cycles that each include a sequence of two distinct modes: a setup mode and a signal acquisition mode. During the setup mode, the n-type quantum well interface and/or the p-type quantum well interface is(are) substantially emptied of charge. During the signal acquisition mode, photocurrent is generated by the thyristor detector device in response to the absorption of incident electromagnetic radiation therein, which can induce the thyristor detector device to switch from an OFF state to an ON state. The OFF/ON state of the thyristor detector device produces an output digital electrical data that corresponds to the amount of incident radiation absorbed by the thyristor detector device during the signal acquisition mode of the current cycle.

Abstract: A method of fabricating a semiconductor device includes the steps of forming (or providing) a series of layers formed on a substrate, the layers including a first plurality of layers including an n-type ohmic contact layer, a p-type modulation doped quantum well structure, an n-type modulation doped quantum well structure, and a fourth plurality of layers including a p-type ohmic contact layer. Etch stop layers are used during etching operations when forming contacts to the n-type ohmic contact layer and contacts to the n-type modulation doped quantum well. Preferably, each such etch stop layer is made sufficiently thin to permit current tunneling therethrough during operation of optoelectronic/electronic devices realized from this structure (including heterojunction thyristor devices, n-channel HFET devices, p-channel HFET devices, p-type quantum-well-base bipolar transistor devices, and n-type quantum-well-base bipolar transistor devices).

Abstract: An array of thyristor detector devices is provided having an epitaxial growth structure with complementary types of modulation doped quantum well interfaces located between a P+ layer and an N+ layer. The thyristor detector devices operate over successive cycles that each include a sequence of two distinct modes: a setup mode and a signal acquisition mode. During the setup mode, the n-type quantum well interface and/or the p-type quantum well interface is(are) substantially emptied of charge. During the signal acquisition mode, photocurrent is generated by the thyristor detector device in response to the absorption of incident electromagnetic radiation therein, which can induce the thyristor detector device to switch from an OFF state to an ON state. The OFF/ON state of the thyristor detector device produces an output digital electrical data that corresponds to the amount of incident radiation absorbed by the thyristor detector device during the signal acquisition mode of the current cycle.

Abstract: An optoelectronic circuit includes a resonant cavity formed on a substrate and into which is injected an input digital optical signal that encodes bits of information (each bit representing an OFF logic level or an ON logic level). A heterojunction thyristor device, formed in the resonant cavity, produces an output digital electrical signal corresponding to the input digital optical signal. A sampling clock defines sampling periods that overlap the bits (e.g., ON/OFF pulse durations) in the input digital optical signal. The sampling clock can be in the form of electrical pulses supplied to the n-channel injector terminal(s) and/or p-channel injector terminals of the heterojunction thyristor device. Alternatively, the sampling clock can be in the form of optical pulses that are part of the Optical IN signal that is resonantly absorbed by the device. The heterojunction thyristor device operates in an OFF state and an ON state.

Abstract: A method of fabricating a semiconductor device includes the steps of forming (or providing) a series of layers formed on a substrate, the layers including a first plurality of layers including an n-type ohmic contact layer, a p-type modulation doped quantum well structure, an n-type modulation doped quantum well structure, and a fourth plurality of layers including a p-type ohmic contact layer. Etch stop layers are used during etching operations when forming contacts to the n-type ohmic contact layer and contacts to the n-type modulation doped quantum well. Preferably, each such etch stop layer is made sufficiently thin to permit current tunneling therethrough during operation of optoelectronic/electronic devices realized from this structure (including heterojunction thyristor devices, n-channel HFET devices, p-channel HFET devices, p-type quantum-well-base bipolar transistor devices, and n-type quantum-well-base bipolar transistor devices).

Abstract: An integrated circuit is provided with a photonic device and a spot-size converter waveguide device integrated on a common substrate. The spot-size converter waveguide device provides for transformation between a larger spot-size and a smaller spot-size corresponding to the photonic device. The spot-size converter waveguide device includes at least one of a bottom mirror and top mirror, which provide highly-reflective lower and upper cladding, respectively, for vertical confinement of light propagating through the waveguide device. The top mirror overlies opposing sidewalls of the spot-converter waveguide device, which provide highly-reflective sidewall cladding for lateral confinement of light propagating through the waveguide device. Advantageously, the highly-reflective lower cladding provided by the bottom mirror limits optical loss of the waveguide device. Similarly, the highly-reflective upper cladding and sidewall cladding provided by the top mirror limits optical loss of the waveguide device.

Abstract: An integrated circuit is provided with a photonic device and a spot-size converter waveguide device integrated on a common substrate. The spot-size converter waveguide device provides for transformation between a larger spot-size and a smaller spot-size corresponding to the photonic device. The spot-size converter waveguide device includes at least one of a bottom mirror and top mirror, which provide highly-reflective lower and upper cladding, respectively, for vertical confinement of light propagating through the waveguide device. The top mirror overlies opposing sidewalls of the spot-converter waveguide device, which provide highly-reflective sidewall cladding for lateral confinement of light propagating through the waveguide device. Advantageously, the highly-reflective lower cladding provided by the bottom mirror limits optical loss of the waveguide device. Similarly, the highly-reflective upper cladding and sidewall cladding provided by the top mirror limits optical loss of the waveguide device.

Abstract: An improved imaging array (and corresponding method of operation) includes a plurality of heterojunction thyristor-based pixel elements disposed within resonant cavities formed on a substrate. Each thyristor-based pixel element includes complementary n-type and p-type modulation doped quantum well interfaces that are spaced apart from one another. Incident radiation within a predetermined wavelength resonates within the cavity of a given pixel element for absorption therein that causes charge accumulation. The accumulated charge is related to the intensity of the incident radiation. The heterojunction-thyristor-based pixel element is suitable for many imaging applications, including CCD-based imaging arrays and active-pixel imaging arrays.

Abstract: Interference caused by the propagation of a transmit signal transmitted from a transmit antenna to a receive antenna is effectively cancelled by an improved signal cancellation system. The system includes an interference cancellation signal generator that generates a time-delayed and amplitude-reduced representation of said transmit signal. A summing stage is operably coupled to the interference cancellation signal generator and the receive antenna. The summing stage subtracts the time-delayed and amplitude-reduced representation of the transmit signal from a receive signal to substantially cancel the interference. The interference cancellation signal generator preferably includes a novel programmable optical delay line that introduces a variable amount of optical delay to an optical signal derived from said transmit signal in addition to a thyristor-based sigma delta modulator that converts samples of the transmit signal to into a digital signal in the optical domain.

Abstract: An optoelectronic circuit includes a resonant cavity formed on a substrate and into which is injected an input digital optical signal that encodes bits of information (each bit representing an OFF logic level or an ON logic level). A heterojunction thyristor device, formed in the resonant cavity, produces an output digital electrical signal corresponding to the input digital optical signal. A sampling clock defines sampling periods that overlap the bits (e.g., ON/OFF pulse durations) in the input digital optical signal. The sampling clock can be in the form of electrical pulses supplied to the n-channel injector terminal(s) and/or p-channel injector terminals of the heterojunction thyristor device. Alternatively, the sampling clock can be in the form of optical pulses that are part of the Optical IN signal that is resonantly absorbed by the device. The heterojunction thyristor device operates in an OFF state and an ON state.

Abstract: A thyristor and family of high speed transistors and optoelectronic devices are obtained on a monolithic substrate (149) with an epitaxial layer structure comprised of two modulation doped transistor structures inverted with respect to each other. The transistor structures are obtained by adding planar doping to the Pseudomorphic High Electron Mobility Transistor (PHEMT) structure. For one transistor, two sheets of planar doping of the same polarity separated by a lightly doped layer are added which are opposite to the modulation doping of the PHEMT. The combination is separated from the PHEMT modulation doping by undoped material. The charge sheets are thin and highly doped. The top charge sheet (168) achieves low gate contact resistance and the bottom charge sheet (153) defines the capacitance of the field-effect transistor (FET) with respect to the modulation doping layer of the PHEMT. For the other transistor, only one additional sheet is added.

Abstract: An integrated circuit (and optical transceiver module) includes an optoelectronic thyristor device formed within a resonant cavity on a substrate, and circuitry integrally formed on the substrate that dynamically switches the thyristor between a transmit mode configuration and a receive mode configuration. In the transmit mode configuration, the thyristor is modulated between a non-lasing state and a lasing state in accordance with an input digital electrical signal. In the receive mode configuration, the thyristor device is modulated between a non-lasing OFF state and a non-lasing ON state in accordance with an input digital optical signal that is injected into the resonant cavity to thereby produce an output digital electrical data signal that corresponds to the input digital optical signal. The integrated circuit (and optical transceiver module) can be used in optical fiber applications as well as free-space applications.

Abstract: An optoelectronic pulse generator is provided that includes a thyristor detector/emitter device having an input port and an output port. The thyristor detector/emitter device is adapted to detect an input optical pulse supplied to the input port and to produce an output optical pulse (via laser emission) and an output electrical pulse in response to the detected input optical pulse. The output optical pulse is output via the output port. An optical feedback path is operably coupled between the output port and the input port of the thyristor detector/emitter device. The optical feedback path supplies a portion of the output optical pulse produced by the thyristor detector/emitter device to the input port, thereby causing the thyristor detector/emitter device to produce a sequence of output optical pulses and a corresponding sequence of output electrical pulses.

Abstract: An optoelectronic circuit includes a resonant cavity formed on a substrate and into which is injected an input digital optical signal that encodes bits of information (each bit representing an OFF logic level or an ON logic level). A heterojunction thyristor device, formed in the resonant cavity, produces an output digital electrical signal corresponding to the input digital optical signal. A sampling clock defines sampling periods that overlap the bits (e.g., ON/OFF pulse durations) in the input digital optical signal. The sampling clock can be in the form of electrical pulses supplied to the n-channel injector terminal(s) and/or p-channel injector terminals of the heterojunction thyristor device. Alternatively, the sampling clock can be in the form of optical pulses that are part of the Optical IN signal that is resonantly absorbed by the device. The heterojunction thyristor device operates in an OFF state and an ON state.