Abstract: A CMOS device fabricated in a silicon-on-insulator structure and including circuitry and methods in a first embodiment dynamically shifts the threshold voltage of the CMOS device in a receiver to provide improved noise margin and in a second embodiment dynamically matches the threshold voltages in a differential amplifier to correct for manufacturing offset. To dynamically shift the threshold voltage for noise immunity, the back gate or bulk nodes of the devices is shifted through two similar circuits comprised of npn inverters with clamping devices. The back gate of the n device is biased at 0 volts for the maximum Vth and is biased at +1 threshold for the minimum Vth of the device. Only the back gate of the p device is biased at Vdd for the maximum Vth of the device and is biased at 1 Vth below Vdd for the minimum Vth of the device. The Vth of the n device and the p device should be less than the forward bias of the respective source volt junctions to prevent unwanted bipolar currents.

Abstract: A low voltage CMOS circuit and method provide output current ability meeting multimode requirements of high voltage off-chip drivers while protecting the CMOS devices from various breakdown mechanisms. The circuit and method utilize intermediate voltages between two power rails and voltage division techniques to limit the voltages to acceptable limits for drain-to-source, gate-to-drain, and gate-to-source of CMOS devices in any chosen technology. The circuit comprises first and second CMOS cascode chains connected between a high voltage power rail, e.g 5 volt and a reference potential power rail, e.g. ground. Each CMOS cascode chain comprises first and second p-type MOS devices in series with first and second n-type MOS devices. An input circuit is coupled to a node at the midpoint of the first CMOS cascode chain. A bias voltage, typically 3.3 volts is connected to the NMOS devices in the first and CMOS cascode chains.

Abstract: A method and apparatus for obtaining near 100 percent quiescent current test coverage within a reasonable amount of time is accomplished by providing a plurality of test circuits interdisposed between a plurality of combinational logic circuits. During testing, the testing circuits isolate the input of one combinational logic circuit from the output of the preceding combinational logic, thus allowing the test circuit to stimulate the input of the combinational logic circuit. By performing the input stimulations of the plurality of combinational logic circuits simultaneously, only two test steps are needed to check the quiescent current of the plurality of combinational logic circuits.

Abstract: A method and apparatus for obtaining near 100 percent quiescent current test coverage within a reasonable amount of time is accomplished by providing a plurality of test circuits interdisposed between a plurality of combinational logic circuits. During testing, the testing circuits isolate the input of one combinational logic circuit from the output of the preceding combinational logic, thus allowing the test circuit to stimulate the input of the combinational logic circuit. By performing the input stimulations of the plurality of combinational logic circuits simultaneously, only two test steps are needed to check the quiescent current of the plurality of combinational logic circuits.

Abstract: A VLSI chip is disclosed having reduced power dissipation. This is accomplished by limiting the output voltage swing at the output of off chip driver circuits by utilization of a control circuit to regulate the gate bias voltage of an NFET pull-up transistor coupled to the output of the driver circuit and by feeding back the output of the driver circuit to the control circuit.

Abstract: A tristate buffer circuit for mixed voltage applications. The circuit is built from field effect transistors and is used as an output buffer in applications where a low voltage component needs to drive both components which are powered by the same low voltage and components which are powered by a higher voltage. The circuit uses a floating n-well technique in combination with a pass-gate network, a one-shot circuit, and a process-dependent bias voltage reference. It is particularly useful on CMOS semiconductor chips which have bus interfaces, such as local area network (LAN) protocol chips.

Abstract: A dual electron injection structure (DEIS) and process for incorporating it into a semi-conductor structure, such as an E2PROM and/or NVRAM, is disclosed. The DEIS includes a composite structure formed from a layer of silicon rich nitride, a layer of silicon dioxide (SiO.sub.2) and a layer of silicon rich oxide. Preferably, a Plasma Enhanced Chemical Vapor Deposit (PECVD) method or a low pressure chemical vapor deposit (LPCVD) method is used to place the DEIS between the Poly 1 and Poly 2 devices of the semi-conductor structure.

Abstract: The invention is an improved on chip low voltage to high voltage converter. A capacitive charge pump circuit driven by an asynchronous inverter is used. The charge pump has improved voltage regulation that automatically compensates for process variation in the required program/erase voltage and for charge trapping in the oxide layer of electrically alterable memory products. A charge trapping material that tracks the charge trapping occurring in memory products is used in a feedback circuit to control the output voltage supply. As charge trapping occurs, the output supply voltage is boosted. This overcomes the effects of charge trapping and provides increased cycles of writing and erasing for a semiconductor memory that suffers from charge trapping in its oxide insulation. A dual electron injector structure is used to monitor the charge trapping effect. A typical one order magnitude increase in the number of write or erase cycles before memory degredation occurs can be achieved with this invention.

Abstract: A process for placing non-continuous Dual Electron Injection Structures (DEIS) between two layers of polysilicon used to form an array of poly devices on an integrated circuit substrate. Separate masks are used to define Poly 1 and Poly 2 devices, respectively. The DEIS structure is disposed above the poly 1 devices. A silicon nitride (Si.sub.3 N.sub.4) layer is used to mask the DEIS structure and prevents it from oxidizing during certain processing steps. A thin layer of poly x is placed between the DEIS structure and the Si.sub.3 N.sub.4. The poly x layer forms a buffer and protects the DEIS during an etching step which removes the Si.sub.3 N.sub.4 layer.

Abstract: High voltage tolerant FET circuits are characterized by the use of shield structures surrounding source/drain diffusion pockets, with the shields tied to apropriate potentials, which in some cases is the associated gate potential. Some embodiments use enhancement mode devices which however have implanted channels underlying the shield structures. Operation of several embodiments is achieved near the snap-back limits by the use of a clamp to maintain potential drop below this limit. High voltage switching at heavy loads is achieved by a voltage divider providing appropriate gate potentials to the load carrying FETs.

Abstract: A vertical PNP bipolar transistor structure with Schottky Barrier diode emitter is disclosed which simplifies the structure and process steps for combining a complementary PNP in an NPN integrated circuit and improves the speed and density of the vertical PNP. The PNP emitter is formed with a Schottky contact such that only the PNP base region is contained in the NPN emitter junction structure. The structure uses a separately masked ion/implant for the NPN intrinsic base implant which also forms the PNP collector region so that the PNP base doping profile can intercept the PNP collector profile at a lower concentration resulting in lower collector/base capacitance, lower series collector resistance and higher collector/base breakdown voltage for the PNP. Since the base doping concentration is lower in the structure and the emitter has no sidewall capacitance, the PNP emitter-base capacitance is greatly reduced. These features result in an improved frequency response for the PNP structure.

Abstract: A reduction in cell area and an improvement in tolerance allowed for programming and erase voltages is achieved utilizing a diffused control gate having improved capacitive coupling to the floating gate through a thin oxide grown on single crystal silicon.

Abstract: A high performance JFET structure and process are disclosed which are compatible with high performance NPN transistors. The high performance JFET is merged in a bipolar/FET device which forms a dense, two level logic function. The JFET can be employed as a switched device or as an active load in a bipolar logic circuit and is formed in the P-type base diffusion of what would otherwise have been an NPN transistor. In the BIFET merged device, the JFET and bipolar transistor share a common base and drain and a common collector and gate in the P-type base region of what would otherwise have been an NPN transistor. Both an NPN type BIFET and an PNP type BIFET are disclosed. The merged JFET and bipolar transistor provide better than a 30% area reduction when compared to their non-merged precursors.

Abstract: A self-isolated Schottky Barrier diode structure and method of fabrication are disclosed for generating a device having controlled characteristics. An opening is made through an oxide layer over a central region of an n-type semiconductor substrate. The opening has inclined sidewalls over an annular region surrounding the central region of the substrate. An n-type dopant layer is ion implanted through the opening and the surrounding oxide layer. This controls the barrier height for the Schottky Barrier diode and controls the lifetime of minority carriers in the outside region of the substrate. This has the effect of minimizing PNP parasitic transistor action. A Schottky Barrier contact is formed in the opening through an oxide layer creating a rectifying junction with the semiconductor substrate in the central region.

Abstract: A self-isolated Schottky Barrier diode structure and method of fabrication are disclosed for generating a device having controlled characteristics. An opening is made through an oxide layer over a central region of an n-type semiconductor substrate. The opening has inclined sidewalls over an annular region surrounding the central region of the substrate. An n-type dopant layer is ion implanted through the opening and the surrounding oxide layer. This controls the barrier height for the Schottky Barrier diode. In the region of the substrate surrounding the annular region, where the ion implantation takes place through the full thickness of the oxide, the lifetime of minority carriers is controlled. This has the effect of minimizing PNP parasitic transistor action. A Schottky Barrier contact is formed in the opening through the oxide layer creating a rectifying junction with the semiconductor substrate in the central region.

Abstract: An improved I.sup.2 L structure and process are disclosed which reduces the minority carrier charge storage, increases the emitter injection efficiency and reduces the emitter diffusion capacitance in the upward injecting vertical NPN transistor and reduces the minority carrier charge storage and increases the collector efficiency in the lateral PNP transistor.

Abstract: A high performance JFET structure and process are disclosed which are compatible with high performance NPN transistors. The high performance JFET is merged in a bipolar/FET device which forms a dense, two level logic function. The JFET can be employed as a switched device or as an active load in a bipolar logic circuit and is formed in the P-type base diffusion of what would otherwise have been an NPN transistor. In the BIFET merged device, the JFET and bipolar transistor share a common base and drain and a common collector and gate in the P-type base region of what would otherwise have been an NPN transistor. Both an NPN type BIFET and an PNP type BIFET are disclosed. The merged JFET and bipolar transistor provide better than a 30% area reduction when compared to their non-merged precursors.

Abstract: A double level metal interconnection structure and process for making same are disclosed, wherein an etch-stop layer is formed on the first metal layer to prevent over-etching thereof when forming the second level metal line in a via hole in an insulating layer thereover, by means of reactive plasma etching. The etch-stop layer is composed of chromium and the reactive plasma etching is carried out with a halocarbon gas.

Abstract: A circuit technique is disclosed for compensating for changes in the resistance of an integrated circuit resistor in an epitaxial bed, which is exposed to temperature changes. The resistance of an integrated circuit resistor is a function of the temperature at which is operates. The invention is based on the recognition that the resistance of the resistor is also a function of the potential difference between the body of the resistor and the epitaxial bed itself. Temperature compensation is achieved by connecting a temperature sensing circuit to the epitaxial bed, which has a voltage output which varies inversely with respect to the temperature coefficient of resistance of the resistor. Thus, the net change in the resistance of the resistor as it undergoes a temperature change, approximates zero.

Abstract: An improved mask fabrication process is disclosed which may be broadly applied to ion-implantation, reactive plasma etching, or the etching of semiconductor structures. The process is based upon the deposition onto an oxide coated or bare semiconductor surface, of a first photoresist layer having formed therein a plurality of windows and which is hardened by a wet chemical technique so as to have an increased resistance to dissolution in solvents. A second photoresist layer is deposited over the surface and windows of the first layer and a subplurality of windows are formed therein over selected windows in the first photoresist layer so as to selectively block a portion of the plurality of windows in the first layer. This composite mask invention may then be employed to carry out an ion-implantation step, wet etching step or reactive plasma etching step on the oxide or semiconductor surface exposed through composite windows.