Abstract: The present disclosure provides techniques for capturing a series of images. In particular, the present disclosure provides techniques for capturing a series of images using a camera integrated with a computing device, such as a cellular phone. A camera may capture a series of images and store the images in a buffer until all images in the series are captured. The images may be transferred to a storage medium after all images in the series are captured. The images may further be processed before being transferred to the storage medium.

Abstract: The invention includes a zebrafish assay for cardiac response.

Abstract: A method and apparatus for efficiently generating complex sinusoids of a desired frequency by multiplying a phasor by a predetermined value once every sampling interval, and using the highest order bits within the phasor to identify if the phasor is at an integer multiple 45 degrees and substituting components in the phasor if it is determined that the phasor is an integer multiple of 45 degrees. If the phasor is not identified as being an integer multiple of 45 degrees then an error factor for both the real and imaginary components is determined and the real and imaginary components are corrected by removing the error factor.

Abstract: A systolic array processor is integrated within a system on chip (SoC) in a format that is compatible with existing and emerging SoC technologies. The systolic array processor may be implemented as a co-processor to a general-purpose digital signal processor or as a functional unit of a very long instruction word (VLIW) processor.

Abstract: A method (400) and apparatus (100) are disclosed for storing the software specifications (320) for each processor (110) in a multi-processor system (100). The disclosed storage technique reduces the total memory space that is required to store the configuration information for each processor (110) and does not require a linear scaling of the memory size when the number of processors increases. Each unique software specification (320) is stored in memory and a pointer (310) is stored for each processor (110) that identifies the corresponding location in memory (140?) of the configuration information for the processor (110). The size of the memory area that stores the pointers (310) for each processor (110) still has a linear relationship with the number of processors (110). The size of the memory area (140?) that stores the unique software specifications (320) is independent of the number of processors (110).

Abstract: A delay addressed data path register file is designed for use in a programmable processor making up a cell in a multi-processor or array signal processing system. The delay addressable register file is particularly useful in, inter alia, adaptive filters where the filter update latency is variable, interpolation filters where the interpolation factor needs to be programmable, and decimation filters where the decimation factor needs to be programmable. The programmability is achieved in an efficient manner, reducing the number of cycles required to perform this task. A single parameter, the “delay limit” value, is programmed at start-up, setting up an internal delay-line within the register file of the processor. Thus, any of the delayed registers can be addressed by specifying the delay index during run-time. The delay line advances one location, modulo “delay-limit”, when the processing loop starts a new iteration.

Abstract: The invention includes a zebrafish assay for cardiac response.

Abstract: A component architecture for digital signal processing is presented. A two dimensional reconfigureable array of identical processors, where each processor communicates with its nearest neighbors, provides a simple and power-efficient platform to which convolutions, finite impulse response (“FIR”) filters, and adaptive finite impulse response filters can be mapped. An adaptive FIR can be realized by downloading a simple program to each cell. Each program specifies periodic arithmetic processing for local tap updates, coefficient updates, and communication with nearest neighbors. During steady state processing, no high bandwidth communication with memory is required.

Abstract: A delay addressed data path register file is designed for use in a programmable processor making up a cell in a multi-processor or array signal processing system. The delay addressable register file is particularly useful in, inter alia, adaptive filters where the filter update latency is variable, interpolation filters where the interpolation factor needs to be programmable, and decimation filters where the decimation factor needs to be programmable. The programmability is achieved in an efficient manner, reducing the number of cycles required to perform this task. A single parameter, the “delay limit” value, is programmed at start-up, setting up an internal delay-line within the register file of the processor. Thus, any of the delayed registers can be addressed by specifying the delay index during run-time. The delay line advances one location, modulo “delay-limit”, when the processing loop starts a new iteration.

Abstract: A method and architecture with which to achieve efficient sub-word parallelism for multiplication resources is presented. In a preferred embodiment, a dual two's complement multiplier is presented, such that an n bit operand B can be split, and each portion of the operand B multiplied with another operand A in parallel. The intermediate products are combined in an adder with a compensation vector to correct any false negative sign on the two's complement sub-product from the multiplier handling the least significant, or lower, p bits of the split operand B, or B[p-1:0], where p=n/2. The compensation vector C is derived from the A and B operands using a simple circuit.

Abstract: The invention concerns a stable control serum or calibration serum containing bilirubin to analytically examine the methodical accuracy of individual parameters in human sera or patients. The control serum or calibration serum according to the invention is used to stabilize bilirubin in solutions and to generally increase the stability of control sera or calibration sera.

Abstract: SLO peptide antigens are described. These peptide antigens are suitable for the determination of SLO antibodies, as immunogens for the production of antibodies against SLO and as vaccines for the production of vaccines against SLO.

Abstract: The invention concerns peptides which have a partial sequence of lipoprotein (a) as well as their use for the purification of antibodies by means of affinity chromatography, as an immunogen for the production of antibodies and as a standard in an immunological test or as a competitive hapten in an agglutination test.

Abstract: SLO peptide antigens are described. These peptide antigens are suitable for the determination of SLO antibodies, as immunogens for the production of antibodies against SLO.