Abstract: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address, (ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

Abstract: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address,(ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

Abstract: A data processor includes execution clusters, an instruction cache, an instruction issue unit, and alignment and dispersal circuitry. Each execution cluster includes an instruction execution pipeline having a number of processing stages, and each execution pipeline is a number of lanes wide. The processing stages execute instruction bundles, where each instruction bundle has one or more syllables. Each lane is capable of receiving one of the syllables of an instruction bundle. The instruction cache includes a number of cache lines. The instruction issue unit receives fetched cache lines and issues complete instruction bundles toward the execution clusters. The alignment and dispersal circuitry receives the complete instruction bundles from the instruction issue unit and routes each received complete instruction bundle to a correct one of the execution clusters. The complete instruction bundles are routed as a function of at least one address bit associated with each complete instruction bundle.

Abstract: For use in a data processor comprising an instruction execution pipeline comprising N processing stages, a system and method of encoding constant operands is disclosed. The system comprises a constant generator unit that is capable of generating both short constant operands and long constant operands. The constant generator unit extracts the bits of a short constant operand from an instruction syllable and right justifies the bits in an output syllable. For long constant operands, the constant generator unit extracts K low order bits from an instruction syllable and T high order bits from an extension syllable. The right justified K low order bits and the T high order bits are combined to represent the long constant operand in one output syllable. In response to the status of op code bits located within a constant generation instruction, the constant generator unit enables and disables multiplexers to automatically generate the appropriate short or long constant operand.

Abstract: There is disclosed a data processor comprising: 1) an instruction execution pipeline comprising N processing stages for executing a load instruction; 2) a status register for storing a modifiable configuration value, the modifiable configuration value having a first value indicating the data processor is capable of executing a misaligned access handling routine and a second value indicating the data processor is not capable of executing a misaligned access handling routine; 3) a misalignment detection circuit for determining if the load instruction performs a misaligned access to a target address of the load instruction and, in response to a determination that the load instruction does perform a misaligned access, generating a misalignment flag; and 4) exception control circuitry capable of detecting the misalignment flag and in response thereto determining if the modifiable configuration value is equal to the first value.

Abstract: A method for clustering the Internet address space employs structural, topological, and temporal clustering techniques. Seedpoints are identified from among network destinations; the seedpoints are topologically clustered into groups; temporal measurements from one or more predetermined locations are made to a seedpoint in each group; and the seedpoints are clustered based on the measurements. The clusters are generalized based on information identifying the network addresses with seedpoints deemed to be close, such as address prefixes in a routing table. A representative is selected for each cluster, such as an intermediate node on a path shared by the seedpoints of the cluster. The technique can be employed by different types of applications, including route selection in an intelligent route controller.

Abstract: A cache flush controller, and an associated method, selectably flushes a memory cache of a data processor. The cache flush controller operates at a memory bus level of the data processor and operates to flush a selected line, or lines of the memory cache by writing arbitrary, selected values to the selected line or lines of the memory cache.

Abstract: A cache flush controller, and an associated method, selectably flushes a memory cache of a data processor. The cache flush controller operates at a memory bus level of the data processor and operates to flush a selected line, or lines of the memory cache by writing arbitrary, selected values to the selected line or lines of the memory cache.

Abstract: For use in a data processor comprising an instruction execution pipeline comprising N processing stages, a system and method of encoding constant operands is disclosed. The system comprises a constant generator unit that is capable of generating both short constant operands and long constant operands. The constant generator unit extracts the bits of a short constant operand from an instruction syllable and right justifies the bits in an output syllable. For long constant operands, the constant generator unit extracts K low order bits from an instruction syllable and T high order bits from an extension syllable. The right justified K low order bits and the T high order bits are combined to represent the long constant operand in one output syllable. In response to the status of op code bits located within a constant generation instruction, the constant generator unit enables and disables multiplexers to automatically generate the appropriate short or long constant operand.

Abstract: There is disclosed bundle alignment and dispersal circuitry for use in a data processor.

Abstract: There is disclosed a data processor comprising: 1) an instruction execution pipeline comprising N processing stages for executing a load instruction; 2) a status register for storing a modifiable configuration value, the modifiable configuration value having a first value indicating the data processor is capable of executing a misaligned access handling routine and a second value indicating the data processor is not capable of executing a misaligned access handling routine; 3) a misalignment detection circuit for determining if the load instruction performs a misaligned access to a target address of the load instruction and, in response to a determination that the load instruction does perform a misaligned access, generating a misalignment flag; and 4) exception control circuitry capable of detecting the misalignment flag and in response thereto determining if the modifiable configuration value is equal to the first value.

Abstract: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address,(ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.