Abstract: Provided are chimeric T cell antigen receptors (TCR) comprising modified TCR chains. The modified TCR chains include fusion polypeptides having one or more heterologous antigen-binding domains fused to the extracellular domain of the TCR chain. Modified TCR chains also include chains that are modified in various other ways including e.g., chain truncation, cysteine modification, domain swapping and combinations thereof. Also provided are nucleic acids encoding the modified TCR chains as well as nucleic acids encoding the chimeric TCRs and recombinant expression vectors comprising such nucleic acids. Immune cells that are genetically modified or otherwise include the described chimeric TCRs, recombinant expression vectors encoding chimeric TCRs, and/or the described nucleic acids are also provided. Methods are also provided, such as methods of killing a target cell and/or treating a subject for a condition, e.g.

Abstract: Defects in the manufacturing of IC devices are analyzed by testing the devices for defects, generating a serial digital data bitstream upon which the test result for each device is encoded in succession, and operating upon the data bitstream to analyze the device defects. This allows for the use of rapid and reliable digital signal processing techniques to perform the analysis. The types of analyses that can be performed include the determination of non-random yields to distinguish random from systematic defects, comparisons with signature defect patterns that correspond to various systematic faults, and yield predictions for other circuits manufactured with a similar process but having a different critical circuit area. An improved windowing technique is used to determine non-random defects, in which normalized defect counts are obtained and compared for various window sizes.

Abstract: An analog-to-digital converter (ADC) generates multiple analog waveforms, preferably as voltage ramps, that progressively increase in signal value over time but at different rates of increase. The ramp with the greatest slope is initially compared with an input signal sample until the ramp exceeds the sample, at which time the system switches to the ramp with the next greatest slope for comparison with the input. The operation then repeats, with the system switching to the next lower ramp each time the current ramp exceeds the input. Both the number of ramp switching events that occur during a sample cycle, and the clock count at the time of the most recent ramp switch, are recorded and used respectively as the most and least significant bits of a digital output. The switching event count proceeds from an initial maximum value from which it subtracts at each switching event, while the clock count builds up from an initial minimum value.