Patents by Inventor Geoffrey Richard Nash

Geoffrey Richard Nash has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8450771
    Abstract: A semiconductor device comprising a plurality of regions of semiconductor material forming a junction at an interface there-between, the junction including a depletion region having a width which varies spatially in at least one direction along the depletion region. Without limitation, the spatial variation in depletion region width is provided by ionised dopants having a concentration which varies spatially along said at least one direction. Alternatively, or in addition, the spatial variation in depletion region width is achieved by varying the thickness of the region(s) of semiconductor spatially along said at least one direction, for example by creating a plurality of cells within said region(s) devoid of said semiconductor material. A method of fabricating a semiconductor device comprising the step of varying the width of the depletion region spatially there-within in at least one direction along the depletion region.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: May 28, 2013
    Assignees: Qinetiq Limited, The Secretary of State for Business Innovation and Skills in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Nothern Ireland
    Inventors: Timothy Ashley, Geoffrey Richard Nash
  • Publication number: 20100171130
    Abstract: A semiconductor device comprising a plurality of regions of semiconductor material forming a junction at an interface there-between, the junction including a depletion region having a width which varies spatially in at least one direction along the depletion region. Without limitation, the spatial variation in depletion region width is provided by ionised dopants having a concentration which varies spatially along said at least one direction. Alternatively, or in addition, the spatial variation in depletion region width is achieved by varying the thickness of the region(s) of semiconductor spatially along said at least one direction, for example by creating a plurality of cells within said region(s) devoid of said semiconductor material. A method of fabricating a semiconductor device comprising the step of varying the width of the depletion region spatially there-within in at least one direction along the depletion region.
    Type: Application
    Filed: December 17, 2009
    Publication date: July 8, 2010
    Applicant: QinetiQ Limited
    Inventors: Timothy Ashley, Geoffrey Richard Nash
  • Patent number: 7589347
    Abstract: A lateral junction semiconductor device and method for fabricating the same comprising the steps of taking a semiconductor structure having a stack formed by a plurality of layers of semiconductor material arranged in a series of substantially parallel planes, the semiconductor material within a first layer having an excess of charge carriers of a first polarity at a first concentration, and selectively removing semiconductor material from the first layer to a depth which varies along a first direction substantially parallel with the planes of the layers within the structure, so as to provide a gradation of the concentration of charge carriers of first polarity within an active layer along the first direction. A photon source comprising said lateral junction semiconductor device.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: September 15, 2009
    Assignee: Qinetiq Limited
    Inventors: Geoffrey Richard Nash, John Henry Jefferson, Keith James Nash