Abstract: A memory, system, and method for providing security for data stored within a memory and arranged within a plurality of memory regions. The method includes receiving an address within a selected memory region and using the address to access an encryption indicator. The encryption indicator indicates whether data stored in the selected memory page are encrypted. The method also includes receiving a block of data from the selected memory region and the encryption indicator and decrypting the block of data dependent upon the encryption indicator.

Abstract: A system. apparatus and method for providing access security for a subject device. The apparatus includes a security check unit (SCU) configured to be coupled to a transmission medium. The SCU is configured to monitor signals on the transmission medium and to detect an attempt by a first device coupled to the transmission medium to access a second device coupled to the transmission medium based upon the signals. The SCU is also configured to determine an identity of the first device based upon the signals and to control access to the second device by the first device dependent upon the identity of the first device. The method includes monitoring signals and detecting an attempt by an additional device to access the subject device based upon the signals. The method also includes using the signals to determine an identity of the additional device and controlling access to the subject device dependent upon the identity of the additional device.

Abstract: A method and apparatus for controlling access to segments of memory having security data stored therein is provided. A security check unit maintains information for a plurality of segments of memory regarding whether each of these plurality of segments has secure data stored therein. A hint directory maintains information regarding whether any of a plurality of these segments has secure data stored therein. The hint directory is capable of bypassing the security check unit when it receives an address that falls within a plurality of the segments that have been indicated as being free from secure data. When the hint directory determines that a received address falls within one of a plurality of segments that contain secure data, then the address is passed to the security check unit for a closer examination.

Abstract: A memory management unit (MMU) is disclosed for managing a memory storing data arranged within a plurality of memory pages. The MMU includes a security check unit (SCU) receiving a linear generated during execution of a current instruction. The linear address has a corresponding physical address residing within a selected memory page. The SCU uses the linear address to access one or more security attribute data structures located in the memory to obtain a security attribute of the selected memory page. The SCU compares a numerical value conveyed by a security attribute of the current instruction to a numerical value conveyed by the security attribute of the selected memory page, and produces an output signal dependent upon a result of the comparison. The MMU accesses the selected memory page dependent upon the output signal. The security attribute of the selected memory page may include a security context identification (SCID) value indicating a security context level of the selected memory page.

Abstract: A method and system for improving memory access in Accelerated Graphics Port systems. The method and system associate a transaction id with individual data transactions within a number of Accelerated Graphics Port (AGP) pipelined data transactions, and identify the individual data transactions within the number of AGP pipelined data transactions via the transaction id. In one instance, the association of a transaction id with individual data transactions includes but is not limited to associating a transaction id with each individual memory read request within a number of AGP pipelined memory read requests and associating an identical transaction id with each individual data unit, within a number of pipelined data units, corresponding to each individual memory read request within the number of AGP pipelined memory requests.

Abstract: A method and system which will increase the ability of memory controllers to intelligently schedule accesses to system memory. The method and system provide a memory controller and a requested memory operation buffer structured so that at least one source attribute of a requested memory operation can be identified. In one instance, the requested memory operation buffer has queues, associated with data buses, which can be utilized to identify source attributes of requested memory operations. Examples of such queues are an Accelerated Graphics Port Interconnect queue associated with an Accelerated Graphics Port interconnect, a system bus queue associated with a system bus, and a Peripheral Component Interconnect bus queue associated with a Peripheral Component Interconnect bus where the queues can be utilized by a memory controller to identify the specific bus from which a requested memory operation originated.

Abstract: A method and system for providing an external locking mechanism for memory locations. The memory includes a first plurality of storage locations configured with BIOS data and a second plurality of storage locations. The second plurality of storage locations includes a first plurality of blocks readable only in SMM and a second plurality of blocks readable in SMM and at least one operating mode other than SMM. The computer system includes a bus, a memory coupled to the bus, and a device coupled to access the memory over the bus. The memory includes a plurality of storage locations, divided into a plurality of memory units. The device includes one or more locks configured to control access to one or more of the plurality of memory units.

Abstract: A communications system includes physical layer hardware and a processing unit. The physical layer hardware is adapted to communicate data over a communications channel in accordance with a plurality of control codes. The physical layer hardware is adapted to demodulate an incoming analog signal to generate a digital receive signal and modulate a digital transmit signal to generate an analog transmit signal. The processing unit is adapted to execute a privileged driver for interfacing with the physical layer hardware. The privileged driver includes program instructions for implementing a protocol layer to decode the digital receive signal, encode the digital transmit signal, and configure the physical layer hardware for receipt of the digital receive signal and transmission of the digital transmit signal based on the plurality of control codes.

Abstract: Methods, devices, and systems for closing back door access mechanisms. A processor includes a first register configured to store one or more hardware-debug-test (HDT) enable bits, a first control logic coupled to receive a plurality of HDT input signals, and a second control logic coupled to the first register. The first control logic is coupled to access the first register. The second control logic is configured to store one or more default values in the first register in response to a reset of the processor. Another processor includes a first control logic coupled to receive a plurality of microcode inputs, a first register coupled to the first control logic, and a second control logic coupled to the first register. The first register is configured to store one or more microcode loader enable bits. The second control logic is configured to store one or more default values in the first register in response to a reset of the processor.

Abstract: A method and system which will provide data processing systems having memory controllers with the ability to intelligently schedule accesses to system memory. The method and system provide a memory controller having a page-state sensitive memory arbiter. The method and system further include one or more memory state tracking units operably coupled to the page-state sensitive memory arbiter, and the one or more memory state tracking units operably coupled to a system memory. The one or more memory state tracking units operably coupled to a system memory further include the one or more memory state tracking units operably coupled to one or more system memory devices. The method and system track system memory status, monitor pending memory access requests, and schedule one or more pending memory access requests for execution dependent upon the system memory status and the pending memory access requests.

Abstract: A computer system includes a peripheral device and a processor complex coupled to the peripheral device. The processor complex is adapted to load a secure driver including program instructions for interfacing with the peripheral device. A method for protecting a software driver includes storing a secure driver in a computer system. The secure driver includes program instructions for interfacing with a peripheral device. The method further includes loading the secure driver; and interfacing with the peripheral device using the secure driver. The peripheral device may be a communications device, such as a software modem.

Abstract: A computer system includes a peripheral device and a processing unit. The processing unit is adapted to execute a driver for interfacing with the peripheral device in a standard mode of operation and an authentication agent in a privileged mode of operation, wherein the authentication agent includes program instructions adapted to authenticate the driver. The peripheral device may comprise a communications device, such as a software modem. A method for identifying security violations in a computer system includes executing a driver in a standard processing mode of a processing unit; transitioning the processing unit into a privileged processing mode; and authenticating the driver in the privileged processing mode. The driver may be adapted for interfacing with a communications peripheral device, such as a software modem.

Abstract: A communications system includes a physical layer hardware unit and a processing unit. The physical layer hardware unit is adapted to communicate data over a communications channel in accordance with assigned transmission parameters. The physical layer hardware unit is adapted to receive an incoming signal over the communications channel and sample the incoming signal to generate a digital received signal. The processing unit is adapted to execute a standard mode driver in a standard mode of operation and a privileged mode driver in a privileged mode of operation. The standard mode driver includes program instructions adapted to extract encrypted data from the digital received signal and pass the encrypted data to the privileged mode driver. The privileged mode driver includes program instructions adapted to decrypt the encrypted data to generate decrypted data including control codes and transfer the control codes to the physical layer hardware unit.

Abstract: A communications system includes a physical layer hardware unit and a processing unit. The physical layer hardware unit is adapted to communicate data over a communications channel. The physical layer hardware unit is adapted to receive unencrypted control codes and encrypted user data over the communications channel and transmit an upstream data signal over the communications channel based on the control codes. The processing unit is adapted to execute a software driver for interfacing with the physical layer hardware unit. The software driver includes program instructions for implementing a protocol layer to decrypt the user data and provide the upstream data to the physical layer hardware unit. A method for configuring a transceiver includes receiving unencrypted control codes over a communications channel; receiving encrypted user data over the communications channel; and transmitting an upstream signal over the communications channel based on transmission assignments defined by the control codes.

Abstract: A communications system includes a physical layer hardware unit and a processing unit. The physical layer hardware unit is adapted to communicate data over a communications channel in accordance with assigned transmission parameters. The physical layer hardware unit is adapted to receive an incoming signal over the communications channel and sample the incoming signal to generate a digital received signal. The processing unit is adapted to execute a standard mode driver in a standard mode of operation and a privileged mode driver in a privileged mode of operation. The standard mode driver includes program instructions adapted to extract control codes from the digital received signal and configure the physical layer hardware assigned transmission parameters based on the control codes.

Abstract: The present invention provides a method and apparatus for securing portions of a memory. The method includes identifying information for protection and indicating at least one physical address of a memory that houses the information as at least one of read and write disabled. The method includes receiving a request from a program to access the information. The method further includes accessing the information in response to determining that the program has the authority to access the information. The apparatus includes a memory comprising a privileged code. The privileged code is capable of receiving a request to protect selected information and indicating at least one physical address of a memory housing the information as at least one of read and write disabled. The privileged code is capable of receiving a request from a program to access the information.

Abstract: A method and system providing a memory controller having a destination-sensitive memory request reordering device. The destination-sensitive memory request reordering device includes a centralized state machine operably connected to one or more memory devices and one or more reorder and bank select engines. The centralized state machine is structured such that control information can be received from at least one of the one or more reorder and bank select engines over the one or more control lines. The centralized state machine is structured such that memory status information can be received from at least one of the one or more reorder and bank select engines over the one or more memory status lines, or such that memory status information can be determined by tracking past memory related activity. Additionally, the centralized state machine is structured to accept memory access requests having associated origin information.

Abstract: A method and system for improving data transmission in data processing systems, especially in the context of data processing systems utilizing the Accelerated Graphics Port (AGP) interface standard. The method and system provide an AGP-enabled device wherein is contained a command queue. The AGP-enabled device is connected to and communicates with an AGP-enabled bridge through and over a data bus. The AGP-enabled bridge has an AGP-enabled device mimicking unit. The AGP-enabled bridge also has an overflow protection unit. In one instance, the AGP-enabled device is an AGP-enabled graphics controller, the command queue is a graphics controller command queue, the AGP-enabled bridge is an AGP-enabled Northbridge, the data bus is an AGP interconnect, and the overflow protection unit is a mimicking buffer overflow detector and routing unit.

Abstract: A method and system for data transmission in data processing systems, especially in the context of data processing systems utilizing the Accelerated Graphics Port (AGP) interface standard. The method and system provide an AGP-enabled device wherein is contained a command queue. The AGP-enabled device is connected to and communicates with an AGP-enabled bridge through and over a data bus. The AGP-enabled bridge has an AGP-enabled device mimicking unit. In one instance, the AGP-enabled device is an AGP-enabled graphics controller, the command queue is a graphics controller command queue, the AGP-enabled bridge is an AGP-enabled Northbridge, and the data bus is an AGP interconnect. In this instance, the graphics controller has a graphics controller full signal unit which controls and utilizes the PIPE# signal of the AGP-enabled graphics controller to indicate whether the graphics controller command queue can accept data.

Abstract: It has been discovered that a method and system can be produced which will, among other things, provide data processing systems having memory controllers with the ability to look ahead and intelligently schedule accesses to system memory. A method and system which improve data processing system memory access. The method and system provide a first-stage origin-sensitive memory access request reordering device, and a second-stage destination-sensitive memory access request reordering device operably coupled to said first-stage origin-sensitive memory access request reordering device. The first-stage origin-sensitive memory access request reordering device receives memory access requests having associated origin information, and reorders the memory access requests based upon the associated origin information.