Abstract: A system and method of ensuring hardware security of a device, such as an integrated circuit having secure data stored thereon. The integrated circuit or other hardware device can implement one or more configurable fuses that limit access to one or more secure locations within the device. The secure locations may contain secure data. The state of the configurable fuses can be ensured, thereby limiting access to secure locations, by forcing the occurrence of a logical state prior to allowing access to hardware locations configured by the fuses. A configurable non-secure access code can be used to force the occurrence of the logical state. Receipt of the non-secure access code by the hardware device forces the occurrence of the hardware state, thereby ensuring access only to those secure locations configured by the fuses.

Abstract: A 3D graphics pipeline includes a prefetch mechanism that feeds a cache of depth tiles. The prefetch mechanism may be predictive, using triangle geometry information from previous pipeline stages to pre-charge the cache, thereby allowing for an increase in memory bandwidth efficiency. A z-value compression technique may be optionally utilized to allow for a further reduction in power consumption and memory bandwidth.

Abstract: In general, this disclosure is directed to circuitry for implementation of headswitches and footswitches in an ASIC for power management. The disclosed circuitry supports not only effective power management, but also efficient use of ASIC area, reduced complexity, and the use of electronic design automation (EDA) tools. In this manner, the disclosed circuitry can support enhanced performance and simplified ASIC design. In some cases, headswitch or footswitch circuitry may be implemented as a switch pad ring that extends around a hard macro forming part of an ASIC core. In other cases, headswitch or footswitch circuitry can be distributed within an ASIC core by embedding distributed headswitch or footswitch components under metal layer power routing coupled to standard cell rows.

Abstract: A method and apparatus are disclosed for a wireless communication device to simultaneously receive at least two signals. Two receiver portions are provided in the wireless communication device. A first receiver portion is configured to receive a first communication signal. A second receiver portion is configured to receive a second communication signal. The two receiver portions are configured to convert the first and second communication signals to a common frequency band. The common frequency band may be an intermediate frequency band or baseband frequency band. The converted first and second communication signals are combined in the common frequency band using an adder or other signal combiner. The combined signal is processed in a single signal processor. The communication device is able to resolve each of the received signals when the first communication signal is a narrowband signal and the second communication signal is a wideband signal, such as a spread spectrum signal.

Abstract: A 3D graphics pipeline includes a prefetch mechanism that feeds a cache of depth tiles. The prefetch mechanism may be predictive, using triangle geometry information from previous pipeline stages to pre-charge the cache, thereby allowing for an increase in memory bandwidth efficiency. A z-value compression technique may be optionally utilized to allow for a further reduction in power consumption and memory bandwidth.

Abstract: Disclosed is a method and apparatus for removing DC offsets in a ZIF radio device, the method including the steps of converting a signal to digital samples, calculating a DC burst by capturing an entire burst and a portion of the adjacent channels, removing DC offset from the digital signal, rotating out frequency error from the digital signal, and performing channel filtering of the digital signal. The system includes a digital DC offset removal circuit, which includes an analog to digital converter, a channel filter connected to the converter, and a rotator system that is connected to the channel filter input and output. The rotator system includes a DC estimator connected to the channel filter input, a DC offset removal component connected to the DC estimator, and a rotator connected to the DC offset removal component, the output of the rotator being connected to the channel filter input.

Abstract: A system and method of ensuring hardware security of a device, such as an integrated circuit having secure data stored thereon. The integrated circuit or other hardware device can implement one or more configurable fuses that limit access to one or more secure locations within the device. The secure locations may contain secure data. The state of the configurable fuses can be ensured, thereby limiting access to secure locations, by forcing the occurrence of a logical state prior to allowing access to hardware locations configured by the fuses. A configurable non-secure access code can be used to force the occurrence of the logical state. Receipt of the non-secure access code by the hardware device forces the occurrence of the hardware state, thereby ensuring access only to those secure locations configured by the fuses.

Abstract: In general, this disclosure is directed to circuitry for implementation of headswitches and footswitches in an ASIC for power management. The disclosed circuitry supports not only effective power management, but also efficient use of ASIC area, reduced complexity, and the use of electronic design automation (EDA) tools. In this manner, the disclosed circuitry can support enhanced performance and simplified ASIC design. In some cases, headswitch or footswitch circuitry may be implemented as a switch pad ring that extends around a hard macro forming part of an ASIC core. In other cases, headswitch or footswitch circuitry can be distributed within an ASIC core by embedding distributed headswitch or footswitch components under metal layer power routing coupled to standard cell rows.

Abstract: A method and apparatus are disclosed for a wireless communication device to simultaneously receive at least two signals. Two receiver portions are provided in the wireless communication device. A first receiver portion is configured to receive a first communication signal. A second receiver portion is configured to receive a second communication signal. The two receiver portions are configured to convert the first and second communication signals to a common frequency band. The common frequency band may be an intermediate frequency band or baseband frequency band. The converted first and second communication signals are combined in the common frequency band using an adder or other signal combiner. The combined signal is processed in a single signal processor. The communication device is able to resolve each of the received signals when the first communication signal is a narrowband signal and the second communication signal is a wideband signal, such as a spread spectrum signal.

Abstract: Disclosed is a method and apparatus for removing DC offsets in a ZIF radio device, the method including the steps of converting a signal to digital samples, calculating a DC burst by capturing an entire burst and a portion of the adjacent channels, removing DC offset from the digital signal, rotating out frequency error from the digital signal, and performing channel filtering of the digital signal. The system includes a digital DC offset removal circuit, which includes an analog to digital converter, a channel filter connected to the converter, and a rotator system that is connected to the channel filter input and output. The rotator system includes a DC estimator connected to the channel filter input, a DC offset removal component connected to the DC estimator, and a rotator connected to the DC offset removal component, the output of the rotator being connected to the channel filter input.