Abstract: A system comprising a processor, a first cache, and a second cache. The processor is configured to perform a processing task according to data stored in a main memory and output a command associated with the processing task. The first cache is located between the processor and the main memory and is configured to store a first portion of the data stored in the main memory and provide a first indication of whether the command has been completed at the first cache. The second cache is located between the first cache and the main memory and is configured to store a second portion of the data stored in the main memory and provide a second indication of whether the command has been completed at the second cache. The processor is configured to perform the processing task in response to receiving both the first indication and the second indication.

Abstract: A data processing system for executing a plurality of instructions having a prescribed program order comprises a register file, a reorder buffer, and a plurality of functional units. The register file includes a plurality of registers to store data. The reorder buffer includes N buffer locations of which M buffer locations are bypassable and N?M buffer locations are non-bypassable, wherein N and M are integers and N>M. Each functional unit is capable of executing instructions regardless of the prescribed program order. The reorder buffer temporarily stores data corresponding to the plurality of instructions. When data of one of the plurality of instructions to be executed by a corresponding one of the plurality of functions units is temporarily stored in one of the M bypassable buffer locations, the reorder buffer transfers the data in one of the bypassable M buffer locations to the corresponding one of the functional units in order to execute the instruction.