Patents by Inventor Georg Ehrentraut
Georg Ehrentraut has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9461004Abstract: A semiconductor workpiece includes a semiconductor substrate, at least two chip areas, components of semiconductor devices being formed in the semiconductor substrate in the at least two chip areas, and a separation trench disposed between adjacent chip areas. The separation trench is formed in a first main surface of the semiconductor substrate and extends from the first main surface to a second main surface of the semiconductor substrate. The second main surface is disposed opposite to the first main surface. The separation trench is filled with at least one sacrificial material.Type: GrantFiled: May 29, 2015Date of Patent: October 4, 2016Assignee: Infineon Technologies Austria AGInventors: Andreas Meiser, Markus Zundel, Martin Poelzl, Paul Ganitzer, Georg Ehrentraut
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Patent number: 9379196Abstract: In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.Type: GrantFiled: February 6, 2014Date of Patent: June 28, 2016Assignee: Infineon Technologies Austria AGInventors: Ravi Joshi, Johannes Baumgartl, Martin Poelzl, Matthias Kuenle, Juergen Steinbrenner, Andreas Haghofer, Christoph Gruber, Georg Ehrentraut
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Publication number: 20160111508Abstract: A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the semiconductor body by an insulation layer, wherein the trench has a top trench portion which extends from the semiconductor surface at least to a depth which is greater than a depth of the first semiconductor area, wherein the trench further has a bottom trench portion extending subsequent to the top trench portion at least up to the second semiconductor area, and wherein the top trench portion has a first lateral dimension and the bottom trench portion has a second lateral dimension which is greater than the first lateral dimension.Type: ApplicationFiled: December 21, 2015Publication date: April 21, 2016Applicant: Infineon Technologies AGInventors: Christian Foerster, Georg Ehrentraut, Frank Pfirsch, Thomas Raker
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Publication number: 20160104797Abstract: A semiconductor device comprises a gate electrode in a trench in a semiconductor body. The gate electrode comprises a plurality of gate segments disposed along an extension direction of the trench, the gate segments being connected to neighboring gate segments by means of connection elements. A distance between adjacent gate segments is equal to or smaller than 0.5*L, wherein L denotes a length of each of the gate segments, the length being measured along the extension direction of the trench.Type: ApplicationFiled: September 30, 2015Publication date: April 14, 2016Applicant: INFINEON TECHNOLOGIES AGInventors: Martin Poelzl, Georg Ehrentraut, Franz Hirler, Maximilian Roesch
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Patent number: 9287376Abstract: An insulated gate trench is manufactured by forming a first dielectric layer on a semiconductor substrate, forming a hardmask on the first dielectric layer and etching a trench into the semiconductor substrate through an opening in the hardmask and the first dielectric layer, the trench having sidewalls and a bottom. The sidewalls and bottom of the trench are lined with a second dielectric layer without an intervening oxide layer along the sidewalls and bottom of the trench. The second dielectric layer is removed from at least part of the bottom of the trench to expose part of the semiconductor substrate, and the exposed part of the semiconductor substrate is removed to form an oxide region at the bottom of the trench. Subsequently, a gate dielectric is formed on the sidewalls and bottom of the trench and a gate electrode in the trench without a separate field electrode in the trench.Type: GrantFiled: December 3, 2014Date of Patent: March 15, 2016Assignee: Infineon Technologies Austria AGInventors: David Laforet, Georg Ehrentraut
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Publication number: 20150262942Abstract: A semiconductor workpiece includes a semiconductor substrate, at least two chip areas, components of semiconductor devices being formed in the semiconductor substrate in the at least two chip areas, and a separation trench disposed between adjacent chip areas. The separation trench is formed in a first main surface of the semiconductor substrate and extends from the first main surface to a second main surface of the semiconductor substrate. The second main surface is disposed opposite to the first main surface. The separation trench is filled with at least one sacrificial material.Type: ApplicationFiled: May 29, 2015Publication date: September 17, 2015Inventors: Andreas Meiser, Markus Zundel, Martin Poelzl, Paul Ganitzer, Georg Ehrentraut
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Publication number: 20150221735Abstract: In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.Type: ApplicationFiled: February 6, 2014Publication date: August 6, 2015Inventors: Ravi Joshi, Johannes Baumgartl, Martin Poelzl, Matthias Kuenle, Juergen Steinbrenner, Andreas Haghofer, Christoph Gruber, Georg Ehrentraut
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Patent number: 9070741Abstract: A semiconductor device is manufactured in a semiconductor substrate comprising a first main surface, the semiconductor substrate including chip areas. The method of manufacturing the semiconductor substrate comprises forming components of the semiconductor device in the first main surface in the chip areas, removing substrate material from a second main surface of the semiconductor substrate, the second main surface being opposite to the first main surface, forming a separation trench into a first main surface of the semiconductor substrate, the separation trench being disposed between adjacent chip areas. The method further comprises forming at least one sacrificial material in the separation trench, and removing the at least one sacrificial material from the trench.Type: GrantFiled: December 17, 2012Date of Patent: June 30, 2015Assignee: Infineon Technologies Austria AGInventors: Andreas Meiser, Markus Zundel, Martin Poelzl, Paul Ganitzer, Georg Ehrentraut
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Patent number: 8803230Abstract: Embodiments described herein relate to semiconductor transistors having trench contacts, in particular to semiconductor transistors having a field electrode below a gate electrode, and to related methods for producing semiconductor transistors having trench contacts.Type: GrantFiled: January 16, 2012Date of Patent: August 12, 2014Assignee: Infineon Technologies Austria AGInventors: Martin Poelzl, Georg Ehrentraut
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Publication number: 20140167209Abstract: A semiconductor device is manufactured in a semiconductor substrate comprising a first main surface, the semiconductor substrate including chip areas. The method of manufacturing the semiconductor substrate comprises forming components of the semiconductor device in the first main surface in the chip areas, removing substrate material from a second main surface of the semiconductor substrate, the second main surface being opposite to the first main surface, forming a separation trench into a first main surface of the semiconductor substrate, the separation trench being disposed between adjacent chip areas. The method further comprises forming at least one sacrificial material in the separation trench, and removing the at least one sacrificial material from the trench.Type: ApplicationFiled: December 17, 2012Publication date: June 19, 2014Inventors: Andreas Meiser, Markus Zundel, Martin Poelzl, Paul Ganitzer, Georg Ehrentraut
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Publication number: 20130181281Abstract: Embodiments described herein relate to semiconductor transistors having trench contacts, in particular to semiconductor transistors having a field electrode below a gate electrode, and to related methods for producing semiconductor transistors having trench contacts.Type: ApplicationFiled: January 16, 2012Publication date: July 18, 2013Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Martin Poelzl, Georg Ehrentraut
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Patent number: 8227340Abstract: A method for producing an electrically conductive connection between a first surface of a semiconductor substrate and a second surface of the semiconductor substrate includes producing a hole, forming an electrically conductive layer that includes tungsten, removing the electrically conductive layer from the first surface of the semiconductor substrate, filling the hole with copper and thinning the semiconductor substrate. The hole is produced from the first surface of the semiconductor substrate into the semiconductor substrate. The electrically conductive layer is removed from the first surface of the semiconductor substrate, wherein the electrically conductive layer remains at least with reduced thickness in the hole. The semiconductor substrate is thinned starting from a surface, which is an opposite surface of the first surface of the semiconductor substrate, to obtain the second surface of the semiconductor substrate with the hole being uncovered at the second surface of the semiconductor substrate.Type: GrantFiled: April 30, 2009Date of Patent: July 24, 2012Assignee: Infineon Technologies AGInventors: Uwe Seidel, Thorsten Obernhuber, Albert Birner, Georg Ehrentraut
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Publication number: 20110309423Abstract: A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the semiconductor body by an insulation layer, wherein the trench has a top trench portion which extends from the semiconductor surface at least to a depth which is greater than a depth of the first semiconductor area, wherein the trench further has a bottom trench portion extending subsequent to the top trench portion at least up to the second semiconductor area, and wherein the top trench portion has a first lateral dimension and the bottom trench portion has a second lateral dimension which is greater than the first lateral dimension.Type: ApplicationFiled: August 25, 2011Publication date: December 22, 2011Applicant: INFINEON TECHNOLOGIES AGInventors: Christian Foerster, Georg Ehrentraut, Frank Pfirsch, Thomas Raker
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Publication number: 20100279503Abstract: A method for producing an electrically conductive connection between a first surface of a semiconductor substrate and a second surface of the semiconductor substrate includes producing a hole, forming an electrically conductive layer that includes tungsten, removing the electrically conductive layer from the first surface of the semiconductor substrate, filling the hole with copper and thinning the semiconductor substrate. The hole is produced from the first surface of the semiconductor substrate into the semiconductor substrate. The electrically conductive layer is removed from the first surface of the semiconductor substrate, wherein the electrically conductive layer remains at least with reduced thickness in the hole. The semiconductor substrate is thinned starting from a surface, which is an opposite surface of the first surface of the semiconductor substrate, to obtain the second surface of the semiconductor substrate with the hole being uncovered at the second surface of the semiconductor substrate.Type: ApplicationFiled: April 30, 2009Publication date: November 4, 2010Inventors: Uwe Seidel, Thorsten Obernhuber, Albert Birner, Georg Ehrentraut
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Publication number: 20080179666Abstract: A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the semiconductor body by an insulation layer, wherein the trench has a top trench portion which extends from the semiconductor surface at least to a depth which is greater than a depth of the first semiconductor area, wherein the trench further has a bottom trench portion extending subsequent to the top trench portion at least up to the second semiconductor area, and wherein the top trench portion has a first lateral dimension and the bottom trench portion has a second lateral dimension which is greater than the first lateral dimension.Type: ApplicationFiled: January 24, 2008Publication date: July 31, 2008Applicant: INFINEON TECHNOLOGIES AGInventors: Christian Foerster, Georg Ehrentraut, Frank Pfirsch, Thomas Raker