Abstract: Semiconductor memories (1) have segmented word lines (5a, 5b), which in each case have a main word line (10a, 10b) made of a conductive metal and a plurality of interconnect segments (15a, 15b) coupled to the main word line (10a, 10b), which are coupled to the respective main word line (10a, 10b) in each case via at least one contact hole filling (11). If one of the contact hole fillings (11) is defective or at high resistance then functional errors of the semiconductor memory occur. The interconnect segments (15a, 15b) of two respective word lines (5a, 5b) can be short-circuited in pairs with the aid of switching units (20), whereby a static current (I) that flows via the contact hole fillings (11) can be used for electrically stressing the contact hole fillings (11). Electrical stressing of contact hole fillings of segmented word lines is thus made possible.

Abstract: An integrated semiconductor memory device includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense amplifier, where each memory cell includes a selection transistor and a storage capacitor. The storage capacitor of each memory cell includes a first capacitor electrode and a second capacitor electrode, and the selection transistor of each memory cell includes a first source/drain region that is connected by a first contact connection to one bit line of a pair of bit lines corresponding with the memory cell, and a second source/drain region that is conductively connected to the first capacitor electrode of the storage capacitor of the memory cell. The second capacitor electrode of the storage capacitor of each memory cell is connected to the other bit line of the pair of bit lines corresponding with the memory cell.

Abstract: A test method for a semiconductor memory device having a bidirectional data strobe terminal for a data strobe signal, and having at least one data terminal for a data signal at a test apparatus, which can at least generate data strobe and data signals and also transfer and evaluate data signals. The memory device is connected to a test apparatus, which generates data strobe and data signals, and transfers and evaluates data signals. In the course of the test using the data strobe and data signals, data are transferred from the first semiconductor memory device to a second semiconductor memory device of identical type and are evaluated after a read-out from the second semiconductor memory device by the test apparatus.

Abstract: An integrated semiconductor memory including memory cells which can be driven via first and second word lines and can be replaced by redundant memory cells. In the first memory cell type, data can be stored corresponding to the data present at a data input terminal. In the memory cells of a second memory cell type, data can be stored inverted with respect to data present at the data input terminal. The integrated semiconductor memory includes a circuit for data inversion, wherein the data are written to a redundant memory cell, inverted with respect to the data present at the data input terminal if the defective memory cell and the redundant memory cell replacing it are situated in different word line strips of a bit line twist, and if the defective memory cell and the redundant memory cell replacing it are associated with different memory cell types.

Abstract: The present invention provides an apparatus for signaling that a predetermined time value has elapsed, having a device for acquiring and storing the amplitude value of a clock signal at an acquisition instant in the temporal profile of the clock signal. A device is provided for continuously comparing the acquired and stored amplitude value of the clock signal with an instantaneous amplitude value of the clock signal and for outputting a comparison signal which has a first logic state if the instantaneous amplitude value of the clock signal is less than the stored amplitude value and has a second logic state if the instantaneous amplitude value of the clock signal is greater than the stored amplitude value.

Abstract: A memory circuit includes a plurality of memory cells, an input/output area for addressing or writing onto the plurality of memory cells by means of electrical signals, and an optical-electrical converter for converting optical signals into the electrical signals, the plurality of memory cells and the input/output area being integrated on a chip, and the optical-electrical converter being mechanically connected to the chip or being integrated into the chip.

Abstract: A housing, in particular for semiconductor devices, a semiconductor device pin, and a method for the manufacturing of pins wherein at least one pin is punched out from a basic body, in particular a lead framed, by means of one or a plurality of punching process steps, wherein the pin is coated with a separate metal layer after the final punching out of said pin.

Abstract: An integrated dynamic memory includes memory cells which are combined to form individual independently addressable units, and a control circuit for controlling a refresh mode for the memory cells. The memory cells can have their memory cell content refreshed. The control circuit is designed such that one or more units of memory cells can be subject to a refresh mode in parallel in a refresh cycle. The control circuit sets a number of memory cell units, which are to be refreshed in parallel in a refresh cycle based on a temperature reference value. A maximum possible operating temperature for a memory chip can be increased without additional restrictions on memory access.

Abstract: An integrated dynamic memory includes memory cells which are combined to form individual independently addressable units, and a control circuit for controlling a refresh mode for the memory cells. The memory cells can have their memory cell content refreshed. The control circuit is designed such that one or more units of memory cells can be subject to a refresh mode in parallel in a refresh cycle. The control circuit sets a number of memory cell units, which are to be refreshed in parallel in a refresh cycle based on a temperature reference value. A maximum possible operating temperature for a memory chip can be increased without additional restrictions on memory access.

Abstract: A housing, in particular for semiconductor devices, a semiconductor device pin, and a method for the manufacturing of pins wherein at least one pin is punched out from a basic body, in particular a lead framed, by means of one or a plurality of punching process steps, wherein the pin is coated with a separate metal layer after the final punching out of said pin.

Abstract: The device according to the invention in each case has a temperature sensor for detecting the temperatures of the memory modules, which is arranged in the memory modules. In addition, a memory control module is provided, which, in order to evaluate the temperatures, is connected to the memory modules via a measurer or means for determining the highest operating temperature of the memory modules. The memory control module is designed and can be operated such that an adaptation operation is initiated, if the highest operating temperature exceeds a specific value.

Abstract: A memory system comprising at least one memory cell in which information can be stored and a refreshing means refreshing the memory cell in predetermined time intervals is provided. In addition, the memory cell comprises a driving means driving the refreshing means in such a way that it only refreshes the memory cell when useful information is stored in the memory cell.

Abstract: A memory circuit includes a plurality of memory cells, an input/output area for addressing or writing onto the plurality of memory cells by means of electrical signals, and an optical-electrical converter for converting optical signals into the electrical signals, the plurality of memory cells and the input/output area being integrated on a chip, and the optical-electrical converter being mechanically connected to the chip or being integrated into the chip.