Abstract: A method of manufacturing semiconductor devices includes defining a sampling plan that contains position information about metrology sites on process wafers. A first property of the process wafers is measured to obtain measurement values at measurement points, wherein a quantity of the measurement points per process wafer is at least tenfold a quantity of the metrology sites. A sampling model that includes at least a wafer model is updated on the basis of the measurement values. The sampling plan is updated on the basis of an assessment of deviations of the measurement values from a current sampling model.

Abstract: A method of manufacturing semiconductor devices includes defining a sampling plan that contains position information about metrology sites on process wafers. A first property of the process wafers is measured to obtain measurement values at measurement points, wherein a quantity of the measurement points per process wafer is at least tenfold a quantity of the metrology sites. A sampling model that includes at least a wafer model is updated on the basis of the measurement values. The sampling plan is updated on the basis of an assessment of deviations of the measurement values from a current sampling model.

Abstract: A method of forming a doped semiconductor portion includes providing a semiconductor substrate with a surface, and providing protruding portions of a covering layer on the substrate surface, where the portions are arranged in a pattern of lines or segments of lines extending in a first direction. Portions of a resist layer are provided on the substrate surface, where the portions of the resist layer are arranged in a pattern of lines or segments of lines extending in a second direction, and the second direction intersects the first direction. The portions of the resist layer have a thickness d, the thickness d being measured perpendicularly with respect to the substrate surface. A tilted ion implantation step is then performed.