Abstract: A microprocessor system includes a central processing unit (CPU) and a nonvolatile memory having a first memory array and a second memory array. A first address register is provided for storing a first address for the first memory array. A second address register is provided for storing a second address for the second memory array. Array select circuitry responsive to an incoming address is provided for selecting the first memory array for a reprogramming operation and the second memory array for a read operation. A multiplexer has inputs coupled to the first memory array and the second memory array for selectively coupling one of the first memory array and the second memory array to an output of the memory. The array select circuitry directs the first address to the first memory array and the second address to the second memory array. The array select circuitry controls the multiplexer to couple the second memory array to the output during the reprogramming operation of the first memory array.

Abstract: A floating gate nonvolatile memory. The memory includes a first memory array and a second memory array. A first address register is provided for storing a first address for the first memory array. A second address register is provided for storing a second address for the second memory array. A multiplexer is coupled to the first memory array and the second memory array at one end and an output of the memory device at the other end for selectively coupling one of the first memory array and the second memory array to the output at a time. Array select circuitry responsive to an incoming address is provided for selecting the first memory array for a reprogramming operation and the second memory array for a read operation. The array select circuitry directs the first address to the first address register and the second address to the second address register.