Patents by Inventor George A. Lerom

George A. Lerom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • I/O cache controller containing a buffer memory partitioned into lines accessible by corresponding I/O devices and a directory to track the lines
    Patent number: 5418927
    Abstract: A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Access authority is checked to determine whether an input/output device is authorized to access that particular page. If it is not, access is denied. Each input/output device has access to a portion of the cache, so that activity by one device will not interfere with activity by another.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: May 23, 1995
    Assignee: International Business Machines Corporation
    Inventors: Albert Chang, George A. Lerom, James O. Nicholson, John C. O'Quin, III, John T. O'Quin, II
  • High speed data transfer system which adjusts data transfer speed in response to indicated transfer speed capability of connected device
    Patent number: 5237676
    Abstract: A computer system bus includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.
    Type: Grant
    Filed: January 13, 1989
    Date of Patent: August 17, 1993
    Assignee: International Business Machines Corp.
    Inventors: Ravi K. Arimilli, Sudhir Dhawan, George A. Lerom, James O. Nicholson, David W. Siegel
  • Data processor having multiple-buffer adapter between a system channel and an input/output bus
    Patent number: 4571671
    Abstract: A data processor has a block-multiplexed system channel coupled to a processing engine and a byte-multiplexed bus coupled to multiple I/O devices. A multi-buffer adapter transfers data by cycle-steal (direct memory access) operations between the channel and the bus. The adapter has multiple buffers switchable to the channel in a burst mode by a channel interface and to the bus in a byte mode by a device-level interface.
    Type: Grant
    Filed: May 13, 1983
    Date of Patent: February 18, 1986
    Assignee: International Business Machines Corporation
    Inventors: Charles S. Burns, Michael R. Crabtree, Dwight A. Gourneau, Scott W. Hinkel, George A. Lerom, Michael J. Mayfield