Abstract: System and methods are provided for detecting helmet contact. A first helmet (e.g., an offensive player's helmet) detects an impact, and transmits a signal indicating the detected impact. A second helmet (e.g., a defensive player's helmet) detects the impact and transmits a signal indicating a detected impact. In response to analyzing the signal transmissions of first and second helmets, a monitor determines that a helmet-to-helmet contact has occurred between the first and second helmets. To minimize the occurrence of false positive determinations, especially in the event that multiple helmets detect impacts, the helmets may be enabled to only transmit a signal if the impact exceeds a first impact threshold. Another means of minimizing false positives is for the helmets to transmit a timestamp associated with a time of impact occurrence. Further, helmets may collect and transmit information regarding the proximity of other helmets.

Abstract: A system and method are provided for using a system-on-chip (SoC) memory manager to optimize the use of off-chip memory modules. A SoC memory controller receives a request for a first data block, subsequent to shutting the first memory down, and determines that the first data block is stored in the first memory. A SoC memory switching core uses a memory map to translate the first data block address in the first memory module to a first data block address in the second memory module. If the first data block is present in an on-SoC cache, the first data block is supplied on the SoC data bus from the cache. Then, the cache is loaded with a plurality of data blocks from a corresponding plurality of addresses in the second memory module, associated with the first data block address.

Abstract: A system and method are provided for using a thermal management core to control temperature on a system-on-chip (SoC). The method provides an SoC with an internal thermal management core and an internal temperature sensor. For example, the sensor may be located on or near a processor core die. The thermal management core monitors temperatures recorded by the SoC temperature sensor, and sends commands for controlling SoC device functions. In response to these commands, the thermal management core monitors a change in the temperature at SoC temperature sensor. The temperature sensor may be monitored via a dedicated SoC internal interface connecting the processor and the thermal management core. Alternately, the thermal management core may poll for temperatures via a system management bus (SMBUS) SoC external interface connecting the processor and thermal management core. Further, a dedicated SoC external alert interface connecting the processor and thermal management core may be monitored.

Abstract: System and methods are provided for detecting helmet contact. A first helmet (e.g., an offensive player's helmet) detects an impact, and transmits a signal indicating the detected impact. A second helmet (e.g., a defensive player's helmet) detects the impact and transmits a signal indicating a detected impact. In response to analyzing the signal transmissions of first and second helmets, a monitor determines that a helmet-to-helmet contact has occurred between the first and second helmets. To minimize the occurrence of false positive determinations, especially in the event that multiple helmets detect impacts, the helmets may be enabled to only transmit a signal if the impact exceeds a first impact threshold. Another means of minimizing false positives is for the helmets to transmit a timestamp associated with a time of impact occurrence. Further, helmets may collect and transmit information regarding the proximity of other helmets.

Abstract: A system and method are provided for adaptively configuring L2 cache memory usage in a system of microprocessors. A system-on-chip (SoC) is provided with a plurality of n selectively enabled processor cores and a plurality of n L2 cache memories. The method associates each L2 cache with a corresponding processor core, and shares the n L2 caches between enabled processor cores. More explicitly, associating each L2 cache with the corresponding processor core means connecting each processor core to its L2 cache using an L2 data/address bus. Sharing the n L2 caches with enabled processors means connecting each processor core to each L2 cache via a data/address bus mesh with dedicated point-to-point connections.

Abstract: A system and method are provided for a system-on-chip (SoC) management module to monitor and dynamically control processor core operating voltages. An SoC is provided with a plurality of processor cores, a plurality of voltage regulators, an internal management module, and at least one temperature sensor. The management module compares monitored temperatures to threshold values, and in response generates voltage commands. The management module sends the voltage commands to the voltage regulators. Each voltage regulator adjusts the operating voltage supplied to a corresponding processor core in response to the voltage commands.

Abstract: A system and method are provided for using a system-on-chip (SoC) memory manager to dynamically shutdown and restart an off-chip memory module. After determining that a memory switch is to be enacted, an SoC memory switching core asserts a hold on processor operations. The memory switching core transfers data from a source memory module to a destination memory module. In a shutdown operation, data is transferred from a first memory module source to an external second memory module destination interfaced to the memory switching core. In a restart operation, data is transferred from the second memory module source to the first memory module destination. The memory switching core uses a memory map for translating the data addresses in the source memory module to data addresses in the destination memory module. Then, the memory switching core deasserts the hold on processor operations.

Abstract: A system and method are provided for using a system-on-chip (SoC) memory speed control logic core to control memory maintenance and access parameters. A SoC is provided with an internal hardware-enabled memory speed control logic (MSCL) core. An array of SoC memory control parameter registers is accessed and a set of parameters is selected from one of the registers. The selected set of parameters is delivered to a SoC memory controller, to replace an initial set of parameters, and the memory controller manages an off-SoC memory using the delivered set of parameters.