Abstract: Organocatalysts can be engineered to mimic biological enzymes for use in a variety of industrially relevant chemical reactions. The organocatalyst comprises a chemical catalyst that is made by imidation of an amine-containing compound to form an N-substituted maleimide and appending the N-substituted maleimide on a furan-containing compound by Diels-Alder reaction and hydrogenation. The N-substituted maleimide may also be made by reacting a protected maleimide and compound containing a primary alkyl halide moiety. The organocatalysts are engineered to append chemical functionalities of amino acids such as glutamic acid for catalyzing hydrolysis of lactose. The organocatalyst further comprises a support to immobilize the chemical catalyst which plays the role of a scaffold to stabilize catalytic active sites and bind the reactants nearby the active sites, similar to a protein scaffold in biological catalysts.

Abstract: Sensors for detecting analytes are disclosed. In various implementations, the sensing device may include a substrate and a sensor array. The sensor array may be arranged on the substrate, and may include a plurality of sensors. In some implementations, at least two of the sensors may include a first carbon-based sensing material disposed between a first pair of electrodes, and a second carbon-based sensing material disposed between a second pair of electrodes. The first carbon-based sensing material may be configured to detect a presence of each analyte of a group of analytes, and the second carbon-based sensing material may be configured to confirm the presence of each analyte of a subset of the group of analytes. In some instances, the group of analytes includes at least twice as many different analytes as the subset of analytes.

Abstract: A semiconductor device includes a backside contact and a substrate. An epitaxial field stop region may be formed on the substrate with a graded doping profile that decreases with distance away from the substrate, and an epitaxial drift region may be formed adjacent to the epitaxial field stop region. A frontside device may be formed on the epitaxial drift region.

Abstract: In some aspects, the techniques described herein relate to a semiconductor device including: a substrate having a first side and a second side, the second side being opposite the first side; active circuitry disposed on the first side of the substrate; a metallic implant disposed in the substrate, the metallic implant being a blanket implant on the second side of the substrate; and a metallic layer disposed on the second side of the substrate, the metallic layer and the second side of the substrate including the metallic implant defining an ohmic contact.

Abstract: In some aspects, the techniques described herein relate to an electronic device including: a substrate; a metallization layer, the metallization layer having: a first surface disposed on the substrate; a second surface opposite the first surface; and a corrosion-prevention implant layer disposed in the metallization layer, the corrosion-prevention implant layer extending from the second surface to a depth from the second surface in the metallization layer, the depth being less than a thickness of the metallization layer; and an electrical connector coupled with the second surface.

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.

Abstract: In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.

Abstract: A method for singulating a semiconductor wafer includes providing the semiconductor wafer having a plurality of semiconductor devices adjacent to a first surface, the plurality of semiconductor devices separated by spaces corresponding to where singulation lines will be formed. The method includes providing an alignment structure adjacent to the first surface and providing a material on a second surface of the semiconductor wafer, wherein the material is absent on the second surface directly below the alignment structure. The method includes passing an IR signal through the semiconductor wafer from the second surface to the first surface where the material is absent to detect the alignment structure and align a singulation device to the spaces where the singulation lines on will be formed.

Abstract: In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.

Abstract: In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.

Abstract: A wire bond system. Implementations may include: a bond wire including copper (Cu), a bond pad including aluminum (Al) and a sacrificial anode electrically coupled with the bond pad, where the sacrificial anode includes one or more elements having a standard electrode potential below a standard electrode potential of Al.

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.

Abstract: A wire bond system. Implementations may include: a bond wire including copper (Cu), a bond pad including aluminum (Al) and a sacrificial anode electrically coupled with the bond pad, where the sacrificial anode includes one or more elements having a standard electrode potential below a standard electrode potential of Al.

Abstract: A wire bond system. Implementations may include: a bond wire including copper (Cu), a bond pad including aluminum (Al) and a sacrificial anode electrically coupled with the bond pad, where the sacrificial anode includes one or more elements having a standard electrode potential below a standard electrode potential of Al.

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.