Patents by Inventor George Diniz

George Diniz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060280055
    Abstract: Signals, such as the +5V signal, the HPD signal, and LOS output from DDC, CEC, or HDMI signals are dynamically monitored, whereby a stand-by mode is entered in the absence of signal activity in any of the above-mentioned dynamically monitored signals. Such a monitoring architecture reduces power dissipation and allows the realization of low-power source/sink architectures.
    Type: Application
    Filed: June 8, 2006
    Publication date: December 14, 2006
    Inventors: Rodney Miller, George Diniz, Barry Stakely, Doug Bartow
  • Publication number: 20050105661
    Abstract: Phase-locked loop structures are provided that facilitate enhanced stability of loop-generated signals. They include an oscillator network, a feedback loop and a controller. The oscillator network generates a loop output signal with a frequency that varies in response to a control voltage and to a frequency-determining parameter, the feedback loop generates the control voltage in response to the loop output signal and a reference signal and the controller increments the frequency-determining parameter to maintain the control voltage within a predetermined control-voltage range. These structures enhance signal stability by facilitating the use of low-gain oscillator structures and they simplify and shorten loop operations because the structures operate in a closed-loop condition at all times.
    Type: Application
    Filed: November 18, 2003
    Publication date: May 19, 2005
    Inventors: Rodney Miller, George Diniz, Ernest Stroud
  • Patent number: 6330296
    Abstract: The present invention provides a delay-locked loop (DLL). The DLL comprises a phase-frequency detector (PFD) for receiving a reference signal. The DLL further includes a charge pump which is coupled to the PFD. The DLL also includes a loop filter which is coupled to the charge pump and the PFD. Additionally in the DLL, delay line means is coupled to the charge pump and the loop filter. The delay line means provides a feedback signal to the PFD. The DLL further includes monitor means coupled to the PFD, the charge pump and the loop filter. The monitor means is for detecting when a voltage across the loop filter is at a predetermined level, wherein when the voltage is at the predetermined level the monitor means causes the PFD to enter a pump-down mode until the feedback signal is aligned with the reference signal. An advantage of the present invention is that DLL loop tracking failures based upon a stuck condition are reliably avoided.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: December 11, 2001
    Assignee: International Business Machines Corporation
    Inventors: Francois Ibrahim Atallah, George Diniz, James Norris Dieffenderfer, David John Seman