Abstract: A method of fabricating a thin film transistor having reduced off-current leakage includes the steps of forming a TFT body with a channel region disposed between a source electrode and a drain electrode and then passivating the exposed portion of the channel region. The passivation includes the steps of wet etching the exposed portions of the channel region in an hydrofluoric acid etchant for a first selected etch time; dry etching the exposed channel region in a reactive ion etching procedure for a second selected etch time; wet etching the channel region again with hydrofluoric acid for a third selected etch time; and then treating the channel region with a cleansing agent, such as photoresist stripper; and annealing the exposed portion of the channel region.

Abstract: Minimum line spacing is reduced and line spacing uniformity is increased in thin film transistors by employing source/drain metallization having a first relatively thin layer of a first conductor and a second relatively thick layer of a second conductor. The second conductor is selected to be one which may be preferentially etched in the presence of the first conductor whereby the first conductor acts as an etch stop for the etchant used to pattern the second conductor portion of the source/drain metallization. This etching is preferably done using dry etching. Dry etching typically provides substantially better control of line width than wet etching. The etching of the second conductor can be done with a dry etch process which etches the photoresist at substantially the same rate as the second conductor whereby the second conductor is provided with a sidewall slope of substantially 45.degree. which improves the quality of passivation provided by subsequent deposition of a conformal passivating layer.

Abstract: A self-aligned, inverted, thin film field effect transistor is produced by patterning the gate electrode to have tapered edges followed by conformal deposition of subsequent layers of the device structure up through a support layer followed by deposition of a subordinate layer such as the source/drain metallization) on the support layer. The subordinate layer itself may be a planarization or non-conformal layer or may have a subsequent non-conformal planarization layer disposed thereon. Thereafter, the structure is non-selectively etched (preferably reactive ion etched) until the support layer is exposed by the creation of an aperture in the subordinate layer in alignment with raised portions of the reference layer while leaving the subordinate layer present on other parts of the structure. Thereafter, the remainder of the device is fabricated with the source and drain electrodes self-aligned with respect to the gate conductor using a selective etch method.

Abstract: A thin film transistor (TFT) having reduced end leakage is fabricated by: forming a gate electrode on a substrate; forming a TFT body disposed over the gate electrode, the TFT body comprising an intrinsic semiconductor material layer, a channel plug disposed on the intrinsic semiconductor material layer over the gate electrode, a doped semiconductor material layer on the intrinsic semiconductor material and the sidewalls of the channel plug, and a source/drain metallization layer; selectively etching the source/drain metallization layer to form an address connection line and a pixel connection line to a respective source electrode tip and drain electrode tip, selectively etching the channel plug to remove the portion of the sidewalls not adjoining the source and electrode tips that had been in contact with the doped semiconductor layer; removing the doped semiconductor layer portion not underlying the address connection line, the pixel connection line, and the source and drain electrode tips; and removing the

Abstract: A collimator for use in an imaging system with a radiation point source is formed from a plurality of collimator plates stacked together. Passages in each collimator plate in conjunction with the respective passages in adjoining plates form a plurality of channels through the collimator. The channel longitudinal axes are aligned with selected orientation angles that correspond to the direct beam path from the radiation source to the radiation detectors. The collimator plates are made up of patterned sheets of radiation absorbent material or alternatively comprise patterned photosensitive material substrates coated with a radiation absorbent material. The cross-sectional shape of each channel corresponds to the cross-sectional shape of the radiation detecting area of the detector element adjoining the channel.

Abstract: A method of fabricating a thin film transistor (TFT) including the steps of forming a gate conductor on a substrate; depositing a gate dielectric layer over the gate conductor; depositing a layer of amorphous silicon over the gate dielectric layer; treating the exposed surface of the amorphous silicon with a hydrogen plasma; depositing a layer of n+ doped silicon over the treated amorphous silicon surface such that an interface is formed between the amorphous silicon and the n+ doped layer that has relatively low contact resistance; depositing a layer of source/drain metallization over the n+ doped layer; and patterning the source/drain metallization and portions of the underlying n+ doped layer to form source and drain electrodes. The TFT material layers are preferably deposited by plasma enhanced chemical vapor deposition.

Abstract: A method of fabricating a thin film transistor (TFT) includes the steps of forming a gate conductor on a substrate; depositing a gate dielectric layer of silicon nitride over the gate conductor; treating the exposed silicon nitride on the surface of the gate dielectric layer with a hydrogen plasma at a power level of at least 44 mW/cm.sup.2 for at least 5 minutes; depositing a layer of amorphous silicon semiconductor material over the gate dielectric layer; depositing a layer of n+ doped silicon over the treated amorphous silicon surface; depositing a layer of source/drain metallization over the n+ doped layer; and patterning the source/drain metallization and portions of the underlying n+ doped layer to form source and drain electrodes. The deposition of the TFT material layers and the hydrogen plasma treatment is preferably by plasma enhanced chemical vapor deposition.

Abstract: The TFT structure formed in accordance with this invention includes a TFT body that has channel plug end sidewalls separated by a distance equal to or less than the width of the source/drain address lines and such that no residual doped semiconductor material adheres to the sidewalls. Similarly, the intrinsic semiconductor material layer is shaped such that no residual doped semiconductor material adheres to the sidewalls of the intrinsic semiconductor material layer underlying the channel plug ends.

Abstract: A collimator for use in an imaging system with a radiation point source is formed from a plurality of collimator plates stacked together. Passages in each collimator plate in conjunction with the respective passages in adjoining plates form a plurality of channels through the collimator. The channel longitudinal axes are aligned with selected orientation angles that correspond to the direct beam path from the radiation source to the radiation detectors. The collimator plates are made up of patterned sheets of radiation absorbent material or alternatively comprise patterned photosensitive material substrates coated with a radiation absorbent material. The cross-sectional shape of each channel corresponds to the cross-sectional shape of the radiation detecting area of the detector element adjoining the channel.

Abstract: A dual dielectric structure is employed in the fabrication of thin film field effect transistors in a matrix addressed liquid display to provide improved transistor device characteristics and also to provide both electrical and chemical isolation for material employed in the gate metallization layer. In particular, the use of a layer of silicon oxide over the gate metallization layer is not only consistent with providing the desired electrical and chemical isolation, but also with providing redundant gate metallization material to be employed beneath source or data lines for electrical circuit redundancy. Gate line redundancy is also possible. The electrical and chemical isolation provided by the dual dielectric layer reduces the possibilities of short circuits occurring in the display. The absence of short circuits together with the improved redundancy characteristics significantly increase manufacturing yield.

Abstract: Minimum line spacing is reduced and line spacing uniformity is increased in thin film transistors by employing source/drain metallization having a first relatively thin layer of a first conductor and a second relatively thick layer of a second conductor. The second conductor is selected to be one which may be preferentially etched in the presence of the first conductor whereby the first conductor acts as an etch stop for the etchant used to pattern the second conductor portion of the source/drain metallization. This etching is preferably done using dry etching. Dry etching typically provides substantially better control of line width than wet etching. The etching of the second conductor can be done with a dry etch process which etches the photoresist at substantially the same rate as the second conductor whereby the second conductor is provided with a sidewall slope of substantially 45.degree. which improves the quality of passivation provided by subsequent deposition of a conformal passivating layer.

Abstract: A large area radiation imager having a scintillator, an amorphous selenium photosensor, and a non-linear high voltage protective device employs a selected biasing voltage between about 100 volts and 1000 volts at the selenium photosensor to cause the photosensor to exhibit avalanche multiplication. The photosensor has an area not less than about 100 square centimeters. The amorphous selenium is doped slightly with arsenic or arsenic and tellurium. The device is advantageously coupled to a data read and reset circuit to selectively read charge generated in pixels of the photosensor. The read and data circuit is protected from an overvoltage condition by the non linear high voltage protective device, such as a protective thin film transistor or a two terminal protective device. The protective TFT is structured to have a relatively thick gate dielectric layer, which thickness is selected to cause the protective TFT to have a threshold voltage corresponding to a desired protective voltage.

Abstract: Positive control over the length of the overlap between the gate electrode and the source and drain electrodes in a thin film transistor is provided by a gate conductor layer comprising two different conductors having differing etching characteristics. As part of the gate conductor pattern definition process, both gate conductors are etched to expose the underlying material and the upper gate conductor layer is etched back to expose the first gate conductor layer in accordance with the desired overlap between the gate electrode and the source and drain electrodes. Thereafter, the remainder of the device is fabricated with the source and drain electrodes self-aligned with respect to the second gate conductor layer using a planarization and non-selective etch method.

Abstract: A dual dielectric structure is employed in the fabrication of thin film field effect transistors in a matrix addressed liquid display to provide improved transistor device characteristics and also to provide both electricial and chemical isolation for material employed in the gate metallization layer. In particular, the use of a layer of silicon oxide over the gate metallization layer is not only consistent with providing the desired electrical and chemical isolation, but also with providing redundant gate metallization material to be employed beneath source or data lines for electrical circuit redundancy. Gate line redundancy is also possible. The electrical and chemical isolation provided by the dual dielectric layer reduces the possibilities of short circuits occurring in the display. The absence of short circuits together with the improved redundancy characteristics significantly increase manufacturing yield.

Abstract: A method for photolithographically forming a mask includes the steps of: forming an island structure of opaque material on a principal surface of a transparent substrate; depositing at least one layer of transparent material on the principal substrate surface and over the island structure; depositing a layer of photoresist material over the at least one transparent layer; exposing a back-side substrate surface, opposite to the principal substrate surface, to UV light to cause exposure of at least a portion of the photoresist, corresponding substantially to an area outside of a shadow of the island structure; reflecting at least a portion of UV light back into the photoresist layer, by depositing a non-specular layer over the photoresist layer before UV exposure, to expose another portion of the photoresist layer a selected overlap distance within the island structure shadow; and removing the exposed photoresist portion to form a mask which is aligned with the island structure and narrower than the island stru

Abstract: A thin-film field-effect-transistor (TFT) includes a gate electrode disposed on a substrate; a first thick layer of silicon nitride is disposed on the substrate and over the gate electrode and a second thinner layer of silicon nitride is disposed on the first layer. The first silicon nitride layer has a silicon-to-nitrogen concentration ratio selected to provide optimum structural characteristics, such as high density, high dielectric strength, low etch rate and the like, to the resulting TFT while the second silicon nitride layer has a silicon-to-silicon concentration ratio selected to provide a good electrical interface between the first silicon nitride layer and a subsequently deposited first layer of amorphous silicon. Another layer of doped amorphous silicon is formed on the first amorphous silicon layer and the second doped layer is patterned to form source and drain regions of the TFT. A source electrode and a drain electrode are respectively disposed in contact with the source and drain regions.

Abstract: A method for fabricating self-aligned thin-film transistors (TFTs) includes the steps of: exposing a backside substrate surface, opposite to a principal substrate surface, to ultra-violet (UV) light to cause exposure of at least a photoresist layer portion which corresponds substantially to an area outside the shadow of a gate electrode formed on the principal substrate surface; developing the exposed photoresist portion to form a mask; etching a second insulation layer segment, using the mask, to form a remaining insulation layer segment, which is aligned with the gate electrode, and narrower than the gate electrode by a selected overlap distance, on each side thereof; and forming source and drain electrodes on a doped semiconductor layer which each overlap the gate electrode by the selected overlap distance. The overlap distance is a function of the UV exposure time, the photoresist development time and the etch time of the second insulation layer.

Abstract: A thin film FET switching element, particularly useful in liquid crystal displays (LCDs) employs particular materials and is fabricated via a particular process to ensure chemical compatibility and the formation of good electrical contact to an amorphous silicon layer while also producing FETs with desirable electrical properties for LCDs. These materials include the use of titanium as a gate electrode material and the use of N.sup.+ amorphous silicon as a material to enhance electrical contact between molybdenum source and drain pads and an underlying layer of amorphous silicon. The process of the present invention provides enhanced fabrication yield and device performance.

Abstract: A thin film FET switching element, particularly useful in liquid crystal displays, employs a set of special materials to ensure compatibility with the indium tin oxide of a pixel electrode layer used as transparent conductive material in liquid crystal display devices. These materials include the use of titanium as a gate electrode material and the use of aluminum as a material to enhance electrical contact between source and drain pads and an underlying layer of amorphous silicon. The apparatus and process of the present invention provide enhanced fabrication yield and device reliability.

Abstract: A digital radiographic imaging system which employs co-operative means for converting the x-rays to an optical image having enhanced quality and detecting said optical image. The x-ray conversion medium employed in the improved radiographic system is positioned physically contiguous to a bi-directional array of electrical charge transfer devices which convert the optical image to an electronic analog representation thereof. Digital information processing means are further included in the improved radiographic system to convert the electronic analog representation of the optical image to a recorded digital representation thereof. The x-ray conversion medium being employed in the improved radiographic system is a high efficiency scintillator body which moves co-operatively with the photo detection means being employed in a further synchronious relationship with a moving fan beam of X radiation being employed to generate the desired optical image after passage through a stationary object.