Abstract: A memory has an ECC-enabled mode and an ECC-disabled mode in which the portion of the memory dedicated to use as storing ECC in the ECC-enabled mode is used for storing general purpose information (data) in the ECC-disabled mode. This is achieved in a non-volatile memory (NVM) by having the data and the portion of the memory with the corresponding ECC on the same word line. This is particularly important in an NVM because of complication relating to erase. In the ECC-enabled mode the ECC and corresponding data should be erased, programmed, and read together in order to avoid a significant layout and performance penalty. This is best achieved by having the ECC and the data on the same word line.

Abstract: A data processing system (10) has an embedded non-volatile memory (22) that is programmed and erased by use of a high voltage provided by a charge pump (78). In order to prevent the non-volatile memory (22) from being inadvertently programmed or erased during low power supply voltage conditions, the charge pump (78) is disabled and discharged when the power supply voltage drops below a predetermined value. This is accomplished by enabling a low voltage detect circuit (110) in response to a program or erase operation being initiated. A control register (76) will provide a high voltage enable signal to the charge pump (78) only when a power supply valid signal is received. In another embodiment, the low voltage detect circuit (110) may be enabled by another condition to protect the data processing system (10) from an authorized access.

Abstract: A single memory array (10) has an isolation circuit for isolating segments of a same bit line (Seg1 BL0, Seg2 BL0) from each other. The isolation circuit (16) permits memory cells located in one segment (12) of an array to be read while memory cells of another segment (14) of the array are being erased. In one example, the isolation circuit (16) electrically couples the segments during a read or program of memory cells located on the second segment (Seg2 BL0). Program information stored in the single memory array may always be accessed while a portion of the same array is erased. Dynamic variation of the size of the isolated bit line segment occurs when multiple isolation circuits are used to create more than two array segments.