Abstract: A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

Abstract: A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

Abstract: A method to selectively cap interconnects with indium or tin bronzes and copper oxides thereof is provided. The invention also provides the interconnect and copper surfaces so formed.

Abstract: A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

Abstract: A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

Abstract: An actuator scaled to macroscopic or microscopic sizes, uses ultrasonic energy to induce motion of an object in a desired direction. The actuator includes one or more pair of piezoelectric transducers connected with a transducer tip. Supplying the piezoelectric transducers with alternating current electrical power causes the tip to vibrate at ultrasonic frequencies. Urging the vibrating tip into contact with a surface on the object at a selected angle of inclination induces the object to move in the desired direction at a rate determined by the inclination angle. Multiple actuators can be used to induce a fall range of movements of variously shaped objects. In microscopic form, the actuator can be used to create a MEMS device. The optional application of a compliant material either on the transducer tip or on the object's surface enhances the movement induced by the actuator.

Abstract: A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 &mgr;m. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.

Abstract: A high density test probe is for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires.

Abstract: Silicon and germanium containing materials are used at surface of conductors in electronic devices. Solder can be fluxlessly bonded and wires can be wire bonded to these surfaces. These material are used as a surface coating for lead frames for packaging integrated circuit chips. These materials can be decal transferred onto conductor surfaces or electrolessly or electrolytically disposed thereon.

Abstract: The disclosure describes a multilayer article of manufacture comprising a substrate having adhered to it a terminally unsaturated adhesive polyimide, where the surface of the adhesive opposite the substrate is adhered to a polyimide, the article further characterized in having one set or a plurality of alternating layers of the terminally unsaturated adhesive polyimide and the polyimide. In another embodiment, the article has at least one adhesive polyimide layer adhered to a metal substrate or an electrical circuit component such as an integrated circuit, or means for forming electrical connections in an electrical circuit such as metal conduits on the circuit or a wiring network embedded within a ceramic and/or polymer substrate.

Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

Abstract: A multilevel electronic package comprising at least two levels, each level including a poly(aryl ether benzimidazole), a polymide and copper. A process of preparing this package is disclosed. Several novel poly(aryl ether benzimidazoles) useful in preparing this package are also set forth.

Abstract: The disclosure describes a multilayer article of manufacture comprising a substrate having adhered to it a terminally unsaturated adhesive polyimide, where the surface of the adhesive opposite the substrate is adhered to a polyimide, the article further characterized in having one set or a plurality of alternating layers of the terminally unsaturated adhesive polyimide and the polyimide. In another embodiment, the article has at least one adhesive polyimide layer adhered to a metal substrate or an electrical circuit component such as an integrated circuit, or means for forming electrical connections in an electrical circuit such as metal conduits on the circuit or a wiring network embedded within a ceramic and/or polymer substrate.In manufacturing the article of manufacture, a surface treatment technique such as wet process or a plasma/optional silane coupling agent may be applied to either the substrate, adhesive polyimide film or polyimide film prior to the bonding operation.

Abstract: The disclosure describes a multilayer article of manufacture comprising a substrate having adhered to it a terminally unsaturated adhesive polyimide, where the surface of the adhesive opposite the substrate is adhered to a polyimide, the article further characterized in having one set or a plurality of alternating layers of the terminally unsaturated adhesive polyimide and the polyimide. the bonding operation.A novel adhesive polyimide is also described which is an adhesive polyimide such as ODPA-APB terminated with unsaturated heterocyclic monoamines such as azaadenines, aminobenzotriazoles, aminopurines or aminopyrazolopyrimidines and optionally anhydrides, aminoacetylenes, vinylamines or amino phosphines. The novel polyimide may also contain unsaturated heterocyclic groups in the polymer backbone or chain, either as a partial or complete replacement for the aromatic diamines used in synthesizing the polyimide.

Abstract: The present invention is directed to a structure for packaging electronic devices, such as semiconductor chips, in a three dimensional structure which permits electrical signals to propagate both horizontally and vertically. The structure is formed from a plurality of assemblies. Each assembly is formed from a substrate having disposed on at least one surface a plurality of electronic devices. Each assembly is disposed in a stack of adjacent assemblies. Between adjacent assemblies there is an electrical interconnection means electrically interconnecting each assembly. The electrical interconnection means is formed from an elastomeric interposer. The elastomeric interposer is formed from an elastomeric material having a plurality of electrical conductors extending therethrough, either in a clustered or un-clustered arrangement. The electrical interconnection means is fabricated having a plurality of apertures extending therethrough.

Abstract: The described invention is directed to microwave methods for burning-in, electrical stressing, thermal stressing and reducing rectifying junction leakage current in fully processed semiconductor chips individually and at wafer level, as well as burning in and stressing semiconductor chip packaging substrates and the combination of a semiconductor chip mounted onto a semiconductor chip packaging substrate. Microwaves burn-in devices in a substantially shorter period of time than conventional burn-in techniques and avoid the need for special workpiece holders which are required by conventional stress and burn-in techniques. Additionally, microwave methods are described for reducing the leakage current of recitfying junctions, such as PN junctions and Schottky barrier diode junctions of semiconductor devices on fully processed semiconductor chips and wafers.

Abstract: A multilevel electronic package comprising at least two levels, each level including a poly(aryl ether benzimidazole), a polymide and copper. A process of preparing this package is disclosed. Several novel poly(aryl ether benzimidazoles) useful in preparing this package are also set forth.

Abstract: The present invention relates to an improved pinless connector for use in microelectronics comprising an improved elastomer resin of polysiloxane and filler.

Abstract: A flex circuit card with an elastomeric cable connector assembly is provided for transmitting high speed signals between two or more printed circuit boards in a high performance computer system. The flex circuit card connects a cable assembly to a printed circuit board. A conductor trace in the flex circuit card extends into an elastomeric end and terminates with a ball shaped contact which is angled to wipe against mating pads on the printed circuit card for making electrical contact. The cable assembly uses multiple wires attached to a plurality of elastomeric connectors. At least one elastomeric connector is attached to each end of the cable assembly and each elastomeric connector has a plurality of contacts which are used to mate with a plurality of pads on the surface of the printed circuit board. The elastomeric connector described in the present invention provides a high density, cable-to-board interconnection that is perpendicular to the surface of the printed circuit board.

Abstract: A flex circuit card with an elastomeric cable connector assembly is provided for transmitting high speed signals between two or more printed circuit boards in a high performance computer system. The flex circuit card connects a cable assembly to a printed circuit board. A conductor trace in the flex circuit card extends into an elastomeric end and terminates with a ball shaped contact which is angled to wipe against mating pads on the printed circuit card for making electrical contact. The cable assembly uses multiple wires attached to a plurality of elastomeric connectors. At least one elastomeric connector is attached to each end of the cable assembly and each elastomeric connector has a plurality of contacts which are used to mate with a plurality of pads on the surface of the printed circuit board. The elastomeric connector described in the present invention provides a high density, cable-to-board interconnection that is perpendicular to the surface of the printed circuit board.