Patents by Inventor George H. Thiel
George H. Thiel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20090200007Abstract: A heat exchanger includes a body having a plurality of cooling fins defining a plurality of channels therebetween. The heat exchanger also includes a valve positioned in a first channel of the plurality of channels. At least a portion of the valve includes a shape memory material having a thermal transformation temperature. The valve is movable between a first discrete position and a second discrete position. Fluid flow is allowed through the first channel when the valve is in the first discrete position above the thermal transformation temperature. Fluid flow is at least partially blocked in the first channel when the valve is in the second discrete position below the thermal transformation temperature.Type: ApplicationFiled: February 13, 2008Publication date: August 13, 2009Applicant: LOCKHEED MARTIN CORPORATIONInventors: Brian W. Foy, George H. Thiel
-
Patent number: 7045562Abstract: A method of self-healing cracks in a cured epoxy base underfill material between an I/C chip and a substrate is provided. A plurality of capsules is dispersed in the epoxy base. Each capsule has a curable thermosetting adhesive encapsulated in a rupturable shell to disperse the thermosetting adhesive in a crack in the epoxy base when the shell ruptures. Each capsule is less than 25 microns in diameter. A curing agent that will cause a reaction of the thermosetting adhesive on contact is dispersed in the epoxy to form a cured adhesive in a crack in said epoxy base. The shell will rupture when encountering a crack being propagated in the underfill material, which will at least partially fill the crack with the adhesive, and cure the adhesive with the curing agent to bond the edges of the crack together. The invention also includes the structure for crack self-healing.Type: GrantFiled: October 16, 2003Date of Patent: May 16, 2006Assignee: International Business Machines CorporationInventor: George H. Thiel
-
Patent number: 7037753Abstract: A semiconductor chip package having a non-planar chip therein, to reduce the stress concentrations between the chip and cover plate. In particular, a chip and method of forming a chip having a non-planar or “domed” back surface, wherein the thickness of the non-planar chip is greatest substantially near the center of the chip. Further, a method of rounding the edges or corners of the chip to reduce crack propagation originating at the edges of the chip.Type: GrantFiled: January 8, 2004Date of Patent: May 2, 2006Assignee: International Business Machines CorporationInventors: William L. Brodsky, Sanjeev B. Sathe, George H. Thiel
-
Patent number: 6967389Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.Type: GrantFiled: December 23, 2003Date of Patent: November 22, 2005Assignee: International Business Machines CorporationInventors: William Infantolino, Voya R. Markovich, Sanjeev B. Sathe, George H. Thiel
-
Publication number: 20040142508Abstract: A semiconductor chip package having a non-planar chip therein, to reduce the stress concentrations between the chip and cover plate. In particular, a chip and method of forming a chip having a non-planar or “domed” back surface, wherein the thickness of the non-planar chip is greatest substantially near the center of the chip. Further, a method of rounding the edges or corners of the chip to reduce crack propagation originating at the edges of the chip.Type: ApplicationFiled: January 8, 2004Publication date: July 22, 2004Inventors: William L. Brodsky, Sanjeev B. Sathe, George H. Thiel
-
Publication number: 20040135245Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.Type: ApplicationFiled: December 23, 2003Publication date: July 15, 2004Applicant: International Business Machines CorporationInventors: William Infantolino, Voya R. Markovich, Sanjeev B. Sathe, George H. Thiel
-
Patent number: 6759270Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.Type: GrantFiled: September 11, 2003Date of Patent: July 6, 2004Assignee: International Buisness Machines CorporationInventors: William Infantolino, Voya R. Markovich, Sanjeev B. Sathe, George H. Thiel
-
Patent number: 6756662Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.Type: GrantFiled: September 25, 2002Date of Patent: June 29, 2004Assignee: International Business Machines CorporationInventors: William Infantolino, Voya R. Markovich, Sanjeev B. Sathe, George H. Thiel
-
Patent number: 6731012Abstract: A semiconductor chip package having a non-planar chip therein, to reduce the stress concentrations between the chip and cover plate. In particular, a chip and method of forming a chip having a non-planar or “domed” back surface, wherein the thickness of the non-planar chip is greatest substantially near the center of the chip. Further, a method of rounding the edges or corners of the chip to reduce crack propagation originating at the edges of the chip.Type: GrantFiled: December 23, 1999Date of Patent: May 4, 2004Assignee: International Business Machines CorporationInventors: William L. Brodsky, Sanjeev B. Sathe, George H. Thiel
-
Publication number: 20040056347Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.Type: ApplicationFiled: September 25, 2002Publication date: March 25, 2004Applicant: International Business Machines CorporationInventors: William Infantolino, Voya R. Markovich, Sanjeev B. Sathe, George H. Thiel
-
Publication number: 20040058474Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.Type: ApplicationFiled: September 11, 2003Publication date: March 25, 2004Applicant: International Business Machines CorporationInventors: William Infantolino, Voya R. Markovich, Sanjeev B. Sathe, George H. Thiel
-
Patent number: 6655020Abstract: A chip carrier package that includes a cover plate attached to the stiffener by a reflowable bonding material is disclosed. Additionally, a thermally and electrically conductive bonding material between the cover plate and the chip itself may be included. Also a chip package including an alignment device to aid in properly aligning the cover plate on the stiffener is disclosed. Furthermore, a method of packaging a chip including providing a reflowable material between the cover plate and stiffener body for attaching the cover plate to the stiffener, and simultaneously attaching the cover plate to the stiffener with an attaching of the carrier to an electronic circuit board is disclosed.Type: GrantFiled: January 26, 2001Date of Patent: December 2, 2003Assignee: International Business Machines CorporationInventors: Timothy F. Carden, Glenn O. Dearing, Kishor V. Desai, Stephen R. Engle, Randall Stutzman, George H. Thiel
-
Patent number: 6649833Abstract: An electronic package is provided including a substrate, a device mounted on the substrate, and a solder member electrically coupling the device to the substrate. The package includes a dielectric material positioned substantially around the solder member which forms a physical connection between the substrate and the device. The volume of the solder member contracts during melting thereof to prevent failure of the physical connection and/or the electrical coupling between the substrate and the device.Type: GrantFiled: August 9, 2002Date of Patent: November 18, 2003Assignee: International Business Machines CorporationInventors: David V. Caletka, Krishna Darbha, Donald W. Henderson, Lawrence P. Lehman, George H. Thiel
-
Patent number: 6552266Abstract: A chip carrier package that includes a cover plate attached to the stiffener by a reflowable bonding material is disclosed. Additionally, a thermally and electrically conductive bonding material between the cover plate and the chip itself may be included. Also a chip package including an alignment device to aid in properly aligning the cover plate on the stiffener. Furthermore, a method of packaging a chip including providing a reflowable material between the cover plate and stiffener body for attaching the cover plate to the stiffener, and simultaneously attaching the cover plate to the stiffener with an attaching of the carrier to an electronic circuit board.Type: GrantFiled: January 26, 2001Date of Patent: April 22, 2003Assignee: International Business Machines CorporationInventors: Timothy F. Carden, Glenn O. Dearing, Kishor V. Desai, Stephen R. Engle, Randall Stutzman, George H. Thiel
-
Patent number: 6552264Abstract: A chip carrier package that includes a cover plate attached to the stiffener by a reflowable bonding material is disclosed. Additionally, a thermally and electrically conductive bonding material between the cover plate and the chip itself may be included. Also a chip package including an alignment device to aid in properly aligning the cover plate on the stiffener. Furthermore, a method of packaging a chip including providing a reflowable material between the cover plate and stiffener body for attaching the cover plate to the stiffener, and simultaneously attaching the cover plate to the stiffener with an attaching of the carrier to an electronic circuit board.Type: GrantFiled: March 11, 1998Date of Patent: April 22, 2003Assignee: International Business Machines CorporationInventors: Timothy F. Carden, Glenn O. Dearing, Kishor V. Desai, Stephen R. Engle, Randall Stutzman, George H. Thiel
-
Publication number: 20020053449Abstract: A chip carrier package that includes a cover plate attached to the stiffener by a reflowable bonding material is disclosed. Additionally, a thermally and electrically conductive bonding material between the cover plate and the chip itself may be included. Also a chip package including an alignment device to aid in properly aligning the cover plate on the stiffener is disclosed. Furthermore, a method of packaging a chip including providing a reflowable material between the cover plate and stiffener body for attaching the cover plate to the stiffener, and simultaneously attaching the cover plate to the stiffener with an attaching of the carrier to an electronic circuit board is disclosed.Type: ApplicationFiled: March 11, 1998Publication date: May 9, 2002Inventors: TIMOTHY F. CARDEN, GLENN O. DEARING, KISHOR V. DESAI, STEPHEN R. ENGLE, RANDALL STUTZMAN, GEORGE H. THIEL
-
Publication number: 20010009197Abstract: A chip carrier package that includes a cover plate attached to the stiffener by a reflowable bonding material is disclosed. Additionally, a thermally and electrically conductive bonding material between the cover plate and the chip itself may be included. Also a chip package including an alignment device to aid in properly aligning the cover plate on the stiffener is disclosed. Furthermore, a method of packaging a chip including providing a reflowable material between the cover plate and stiffener body for attaching the cover plate to the stiffener, and simultaneously attaching the cover plate to the stiffener with an attaching of the carrier to an electronic circuit board is disclosed.Type: ApplicationFiled: January 26, 2001Publication date: July 26, 2001Inventors: Timothy F. Carden, Glenn O. Dearing, Kishor V. Desai, Stephen R. Engle, Randall Stutzman, George H. Thiel
-
Publication number: 20010009196Abstract: A chip carrier package that includes a cover plate attached to the stiffener by a reflowable bonding material is disclosed. Additionally, a thermally and electrically conductive bonding material between the cover plate and the chip itself may be included. Also a chip package including an alignment device to aid in properly aligning the cover plate on the stiffener is disclosed. Furthermore, a method of packaging a chip including providing a reflowable material between the cover plate and stiffener body for attaching the cover plate to the stiffener, and simultaneously attaching the cover plate to the stiffener with an attaching of the carrier to an electronic circuit board is disclosed.Type: ApplicationFiled: January 26, 2001Publication date: July 26, 2001Inventors: Timothy F. Carden, Glenn O. Dearing, Kishor V. Desai, Stephen R. Engle, Randall Stutzman, George H. Thiel
-
Patent number: 6235994Abstract: A multi-layer printed circuit board including at least one layer of an electrically conducting material and at least one layer of an electrically insulating material. At least one through hole formed at least through the at least one layer of electrically conducting material. The at least one through hole includes a material plated on an interior surface thereof. At least one thermal break is provided in the at least one layer of electrically conducting material, such that heat passing between the through hole and the at least one layer of electrically conducting material passes through the at least one thermal break. At least one electrical connection provided in the at least one layer of electrically conducting material between the material plated on the interior surface of the through hole and the at least one layer of electrically conducting material. At least a portion of the at least one electrical connection is between the through hole and the at least one thermal break.Type: GrantFiled: June 29, 1998Date of Patent: May 22, 2001Assignee: International Business Machines CorporationInventors: Bruce J. Chamberlin, Mitchell G. Ferrill, Randall J. Stutzman, George H. Thiel