Abstract: A data processing system including a plurality of control units, a first and second one of which have identical addresses. Both the first and second control units have like designated positions to which peripheral devices may be coupled. In addition the control units are coupled to transfer information between each other over a common electrical bus. The devices coupled to first and second control units are coupled to different designated positions in each of the first and second control units.

Abstract: A central processing system which includes a plurality of units coupled over a common electrical bus for the transfer of information between any two units, includes one unit in which there is a shareable resource such as a memory for example. Apparatus is provided for any units to share such resource. Further apparatus is provided for enabling any of such units so sharing the resource to lock out any other unit which presents a specified control signal to the unit incorporating the resource.

Abstract: A data processing system includes a plurality of units coupled to transfer information over a common bus having an address portion and a data portion. The use of parity bits is made unnecessary by use of both the address and data portion to essentially transfer the same information during a two cycle operation wherein information is transferred from one unit to the other and in response thereto information is transferred back to the first unit. Such information transferred by the first unit over the data portion is effectively returned by the receiving unit over the address portion. Such first unit includes logic for determining whether or not the transferred information is effectively the same as that received from the other unit.

Abstract: In a data processing system having a plurality of units coupled for the transfer of information therebetween over a common electrical bus during asynchronously generated information bus transfer cycles, the units are coupled in a priority network and depending upon their respective priority may gain access to the bus before a lower priority unit is so enabled. Each one of the units includes apparatus for responding to a request for the transfer of information from another unit by providing any one of up to three signal responses including a positive acknowledge signal indicating an immediate response, a negative acknowledge signal indicating that the unit will most likely be busy for a relatively extended period of time and a quasi-negative response indicating that the unit will probably be ready during the next asynchronously generated bus transfer cycle.

Abstract: A magnetic tape subsystem includes a peripheral controller which processes data signals of a block received during the reading and recording of the block on a magnetic tape medium by a selected one of a plurality of magnetic tape devices in response to commands received from a data processing system. The peripheral controller includes a data recovery unit having a plurality of storage indicators. These indicators are set by the controller in accordance with the characteristics of the block of data signals recovered by the data recovery unit providing indications of the results of the reading or recording operation performed by the selected magnetic tape device during the peripheral controller's execution of the command. The controller divides up the interval of time of an operation into a number of time periods and monitors the characteristics of the signals of a block which should be received by the data recovery unit during those intervals.

Abstract: A peripheral subsystem includes error detection apparatus for verifying whether "speed constants" applied thereto have been decoded properly and contain legal codes. The detection apparatus includes binary to decimal decoder circuits which receive the binary coded speed constants and generate a predetermined output signal on one of a plurality of output terminals of the decoder circuits. A selected number of output terminals of the binary to decimal decoder circuits which are less than one half of the total output terminals are applied as inputs to an odd-even check circuit. When each of the constants are decoded without error and contain a legal code, the decoder circuits provide signals to the check circuit which produce a predetermined check signal to indicate that the constant has been decoded properly by the decoder circuits and contains a legal code.