Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.

Abstract: The present disclosure relates to methodologies for designing semiconductor structures, and, more particularly, creating a methodology to connect contacts of semiconductor elements to a metal line using marker tabs to reserve space for future connections between the contacts and the metal line, and then reassigning the marker tabs to connections between the contacts and the metal line on different levels of a metal stack formed over the semiconductor elements.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.

Abstract: The present disclosure relates to methodologies for designing semiconductor structures, and, more particularly, creating a methodology to connect contacts of semiconductor elements to a metal line using marker tabs to reserve space for future connections between the contacts and the metal line, and then reassigning the marker tabs to connections between the contacts and the metal line on different levels of a metal stack formed over the semiconductor elements.

Abstract: A semiconductor device includes a layer of semiconductor material having an active transistor region defined therein, an isolation trench formed in the semiconductor material adjacent the active transistor region, and a trench liner lining the isolation trench, wherein the trench liner is formed from a material that substantially inhibits formation of high-k material thereon, and wherein the isolation trench and the trench liner together form a lined trench. The device has an insulating material in the lined trench, and high-k gate material overlying at least a portion of the insulating material and overlying at least a portion of the active transistor region, such that the trench liner divides and separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region.

Abstract: A semiconductor device includes a layer of semiconductor material having an active transistor region defined therein, an isolation trench formed in the semiconductor material adjacent the active transistor region, and a trench liner lining the isolation trench, wherein the trench liner is formed from a material that substantially inhibits formation of high-k material thereon, and wherein the isolation trench and the trench liner together form a lined trench. The device has an insulating material in the lined trench, and high-k gate material overlying at least a portion of the insulating material and overlying at least a portion of the active transistor region, such that the trench liner divides and separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region.

Abstract: A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.

Abstract: A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.

Abstract: A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.

Abstract: Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate, a short channel (SC) device, and a long channel (LC) device. The short channel device includes an SC gate insulator overlying a first portion of the substrate, an SC metal gate overlying the SC gate insulator, a polycrystalline silicon layer overlying the metal gate, and a silicide layer formed on the polycrystalline silicon layer. The long channel (LC) device includes an LC gate insulator overlying a second portion of the substrate and an LC metal gate overlying the LC gate insulator. An etch stop layer overlies an upper surface of the substrate, and an interlayer dielectric overlies an upper surface of the etch stop layer. An SC cap is disposed in the interlayer dielectric, overlies the SC device, and is formed substantially from the same metal as is the LC metal gate.

Abstract: A method is provided for manufacturing an integrated circuit including a short channel (SC) device and a long channel (LC) device each overlaid by an interlayer dielectric. The SC device has an SC gate stack and the LC device initially has a dummy gate. In one embodiment, the method includes the steps of removing the dummy gate to form an LC device trench, and depositing metal gate material over the SC device and the LC device. The metal gate material contacts the SC gate stack and substantially fills the LC device trench.

Abstract: A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.

Abstract: Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate, a short channel (SC) device, and a long channel (LC) device. The short channel device includes an SC gate insulator overlying a first portion of the substrate, an SC metal gate overlying the SC gate insulator, a polycrystalline silicon layer overlying the metal gate, and a silicide layer formed on the polycrystalline silicon layer. The long channel (LC) device includes an LC gate insulator overlying a second portion of the substrate and an LC metal gate overlying the LC gate insulator. An etch stop layer overlies an upper surface of the substrate, and an interlayer dielectric overlies an upper surface of the etch stop layer. An SC cap is disposed in the interlayer dielectric, overlies the device, and is formed substantially from the same metal as is the LC metal gate.

Abstract: A method is provided for manufacturing an integrated circuit including a short channel (SC) device and a long channel (LC) device each overlaid by an interlayer dielectric. The SC device has an SC gate stack and the LC device initially has a dummy gate. In one embodiment, the method includes the steps of removing the dummy gate to form an LC device trench, and depositing metal gate material over the SC device and the LC device. The metal gate material contacts the SC gate stack and substantially fills the LC device trench.

Abstract: According to one exemplary embodiment, a method for integrating first and second metal layers on a substrate to form a dual metal NMOS gate and PMOS gate comprises depositing a dielectric layer over an NMOS region and a PMOS region of the substrate. The method further comprises depositing the first metal layer over dielectric layer. The method further comprises depositing the second metal layer over the first metal layer. The method further comprises implanting nitrogen in the NMOS region of substrate and converting a first portion of the first metal layer into a metal oxide layer and converting a second portion of the first metal layer into metal nitride layer. The method further comprises forming the NMOS gate and the PMOS gate, where the NMOS gate comprises a segment of metal nitride layer and the PMOS gate comprises a segment of the metal oxide layer.

Abstract: According to one embodiment, a memory cell structure comprises a semiconductor substrate, a first silicon oxide layer situated over the semiconductor substrate, a charge storing layer situated over the first silicon oxide layer, a second silicon oxide layer situated over the charge storing layer, and a gate layer situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer. The reduced charge loss in the charge storing layer has the benefit of reducing threshold voltage shifts, programming data loss, and programming capability loss in the memory device, thereby improving memory device performance.

Abstract: According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate comprises a step of forming a high-k dielectric layer over the substrate. The high-k dielectric layer may be, for example, hafnium oxide or zirconium oxide. The method further comprises forming a first polysilicon layer over the high-k dielectric layer, where the first polysilicon layer is formed by utilizing a precursor does not comprise hydrogen. The first polysilicon layer can have a thickness of between approximately 50.0 Angstroms and approximately 200.0 Angstroms, for example. According to this exemplary embodiment, the method can further comprise forming a second polysilicon layer over the first polysilicon layer. The second polysilicon layer may be formed, for example, by utilizing a precursor that comprises hydrogen, where the first polysilicon layer prevents the hydrogen from interacting with the high-k dielectric layer.

Abstract: According to one exemplary embodiment, a method for integrating first and second metal layers on a substrate to form a dual metal NMOS gate and PMOS gate comprises depositing a dielectric layer over an NMOS region and a PMOS region of the substrate. The method further comprises depositing the first metal layer over dielectric layer. The method further comprises depositing the second metal layer over the first metal layer. The method further comprises implanting nitrogen in the NMOS region of substrate and converting a first portion of the first metal layer into a metal oxide layer and converting a second portion of the first metal layer into metal nitride layer. The method further comprises forming the NMOS gate and the PMOS gate, where the NMOS gate comprises a segment of metal nitride layer and the PMOS gate comprises a segment of the metal oxide layer.

Abstract: Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices are formed by a salicide process wherein a blanket nickel layer is formed in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers. Embodiments include forming the blanket layer of nickel is formed by the sequential steps of: (i) forming a layer of nickel by sputtering with oxygen gas; and, (ii) forming a layer of nickel by sputtering with argon gas. The two step process for forming the blanket layer of nickel advantageously prevents the formation of nickel silicide on the outer surfaces of the insulative sidewall spacers.