Abstract: Time-interleaved analog-to-digital converters (ADCs) and related methods are disclosed that are based upon multiplying digital-to-analog converters (MDACs). For one ADC embodiment, a sample-and-hold circuit receives an input signal and outputs a voltage that represents the input signal. An MDAC receives the voltage, outputs an N-bit digital value, and outputs a current that represents the voltage. A phased current generator receives the current and outputs time-interleaved currents that are based upon the current. An array of sub-ADCs receive the time-interleaved currents, and each sub-ADC outputs a digital value. The digital values from the array of sub-ADCs are then combined and to output an M-bit digital value. The N-bit digital value and the M-bit digital value provide a digital conversion output for the ADC.

Abstract: Current controlled multiplying digital-to-analog converters (MDACs) and related methods are disclosed for time-interleaved analog-to-digital converters (ADCs). For one embodiment, a circuit includes an MDAC having an amplifier that converts a voltage to an output current, a variable load that is dependent upon a digital value and that controls the output current from the amplifier, and an array of comparators that receive the voltage and output the digital value to the variable load. The digital value represents at least a portion of a digital conversion of the voltage. Further, the circuit can include a phased current generator that receives the output current and generates time-interleaved currents where each time-interleaved current is a sampled copy of the output current.

Abstract: Digital calibration systems and related methods are disclosed for multi-stage analog-to-digital converters (ADCs). For one embodiment, a multi-stage ADC includes an initial ADC, an additional ADC, and calibration logic. The initial ADC generates an output signal and N-bit digital values that are based upon an input signal. The additional ADC receives the output signal from the initial ADC and generates M-bit digital values that are based upon the output signal. The calibration logic receives the N-bit digital values and the M-bit digital values and generates correction values. The correction values are based upon differences between maximum values and minimum values for M-bit digital values associated with different regions determined by the N-bit digital values. Digital conversion outputs for the multi-stage ADC are provided as combinations of the N-bit digital values and the M-bit digital values corrected with the correction values.

Abstract: Some embodiments include a system. The system includes a sensor device having a sensor element having a sensor output and an amplification element having at least one amplification stage, an amplifier input, and an amplifier output. The sensor output can be coupled to the amplifier input. Further, each amplification stage of the amplification stage(s) can have at least four thin film transistors, an input node, and an output node. Meanwhile, the sensor element can detect a physical quantity and/or an event and can provide an electric signal to the amplification element in response to detecting the physical quantity and/or the event, and the amplification element can amplify the electric signal received from the sensor element. Other embodiments of related systems and methods are also disclosed.

Abstract: A multi-rate cascaded continuous-time analog-to-digital converter has a plurality of sigma-delta modulator stages and includes first and second continuous-time sigma-delta modulators, and a summation element. The first continuous-time sigma-delta modulator operates at a first sampling rate. The second continuous-time sigma-delta modulator operates at a second sampling rate higher than the first sampling rate. The second continuous-time sigma-delta modulator has a continuous-time voltage controlled oscillator (VCO) quantizer, and a feedback loop coupled between the input and the output. The second continuous-time sigma-delta modulator is cascaded with the first continuous-time sigma-delta modulator. The summation element has inputs coupled to outputs of the first and second continuous-time sigma-delta modulators.

Abstract: Some embodiments include a system. The system includes a sensor device having a sensor element having a sensor output and an amplification element having at least one amplification stage, an amplifier input, and an amplifier output. The sensor output can be coupled to the amplifier input. Further, each amplification stage of the amplification stage(s) can have at least four thin film transistors, an input node, and an output node. Meanwhile, the sensor element can detect a physical quantity and/or an event and can provide an electric signal to the amplification element in response to detecting the physical quantity and/or the event, and the amplification element can amplify the electric signal received from the sensor element. Other embodiments of related systems and methods are also disclosed.