Abstract: Aspects of the invention relate to techniques for repairing layout design defects after layout data have been processed by resolution enhancement techniques. The repair process first determines a re-correction region that includes three portions: core, transition and visible portions. An inverse lithography process is then performed on the core and transition portions of the re-correction region while taking into account effects from the visible portion to generate a modified re-correction region. The transition portion is processed based on distance from boundary between the transition portion and the core portion such that layout features near the boundary between the transition portion and the core portion are adjusted more than layout features farther away from the boundary.

Abstract: An integrated circuit verification system provides an indication of conflicts between an OPC suggested correction and a manufacturing rule. The indication specifies which edge segments are in conflict so that a user may remove the conflict to achieve a better OPC result. In another embodiment of the invention, edge segments are assigned a priority such that the correction of a lower priority edge does not hinder a desired OPC correction of a higher priority edge.

Abstract: An integrated circuit verification system provides an indication of conflicts between an OPC suggested correction and a manufacturing rule. The indication specifies which edges segments are in conflict so that a user may remove the conflict to achieve a better OPC result. In another embodiment of the invention, edge segments are assigned a priority such that the correction of a lower priority edge does not hinder a desired OPC correction of a higher priority edge.

Abstract: One or more control points are identified within a reticle layout that is used in a simulation of a manufacturing process for an integrated device layer. Further, a current geometrical layout pattern is determined in the vicinity of the control points, and a cache is searched for a matching geometrical layout pattern. If the search is successful, a simulation result associated with the matching geometrical layout pattern is retrieved from the cache and reused for the current geometrical layout pattern. Alternatively, if the search is unsuccessful, a simulation result associated with the current geometrical design pattern is computed and stored in the cache for future reuse.

Abstract: An edge-smoothing process identifies a target edge fragment among a number of edge fragments that form a feature in a photolithographic design. Each of the edge fragments has a length and a classification. The length of the target edge fragment is less than a minimum scatter bar length. The target edge fragment is also classified so that it will receive a scatter bar, and the target edge fragment has a collinear edge fragment. The target edge fragment is smoothed in conjunction with the collinear edge fragment to increase the length of the target edge fragment.

Abstract: One or more control points are identified within a reticle layout that is used in a simulation of a manufacturing process for an integrated device layer. Further, a current geometrical layout pattern is determined in the vicinity of the control points, and a cache is searched for a matching geometrical layout pattern. If the search is successful, a simulation result associated with the matching geometrical layout pattern is retrieved from the cache and reused for the current geometrical layout pattern. Alternatively, if the search is unsuccessful, a simulation result associated with the current geometrical design pattern is computed and stored in the cache for future reuse.