Abstract: A method and implementing structures for a domino block circuit configuration includes a plurality of domino logic blocks including inverter circuits to provide inverted signals which are needed for a comprehensive logic analysis and processing. A plurality of clocking signals are applied at various clocking inputs throughout the circuit. The clocking signals are timed relative to each other in a timing sequence to assure that the logic circuit evaluations occur only after relevant data and switching signals have stabilized.

Abstract: A memory array of a plurality of memory cells accessed by either a single-ended wordline or a differential pair of wordlines emanating from a wordline decoder is improved by the inclusion of a sense amplifier circuit on the far end of the memory array from the wordline decoder, which operates to amplify the wordline signals.

Abstract: A memory and a method for communicating therewith are implemented, the memory having a plurality of memory cell groups. Each memory cell group contains a plurality of memory cells. Memory cell groups within each subset of a plurality of subsets of memory cell groups include the same predetermined number of memory cells. During a read operation, a local bitline associated with the memory cell group from which data is being read is coupled to a global bitline. Other local bitlines, associated with the memory cell groups not being accessed during the read are decoupled from the global bitlines. Following a read, the local and global bitlines are restored by a precharge operation.

Abstract: An improved topology for multi-port memory cell layouts in which two or more bitline pairs are required for data transfers is provided. Bitlines are displaced vertically, rather than horizontally. Such vertical spacing provides improved silicon density while reducing bitline capacitance of a memory cell. Additionally, the use of vertically separated bitline pairs allows traditional transitional phase relationships between multi-port operations in multi-port memory implementations. To nullify any sensitivity to an overlapping restore operation, this improved topology includes cross-coupled ports.

Abstract: The data processing system of the present invention implements a multi-port memory cell, wherein the port functions are divided based on a timing cycle in which they may be accessed. For example, in one case, a first port may be utilized only for read operations and accessed only during a first portion of the timing cycle. Similarly, a second port may be used for read or write operations a and may be accessed only during a second portion of the timing cycle. To ensure that the multi-port memory cell functions correctly, both ports should not be accessed simultaneously. A circuit and method are implemented to ensure that both ports are not accessed simultaneously by implementing a delay function in a unique and useful manner.

Abstract: A five transistor memory cell, is a single ended static random access memory (SRAM) cell. Reading and writing from the cell is implemented with one bit line along with word line read and word line write signals. One of the transistors within the memory cell is not coupled directly to ground, but is instead coupled to a controlled impedance node. This permits the affected transistor to float between ground and a high impedance state, which permits one bit line to write into the memory cell.

Abstract: A cache sub-array method and apparatus for use in microprocessor integrated circuits. A processor unit is disposed within a central region of the microprocessor integrated circuit; a peripheral region is designated as a cache memory array region and surrounds the central region; a predetermined number of cache memory sub-arrays are placed in the peripheral region such that variable size cache memory arrays may be efficiently created. The cache memory sub-arrays contain a fixed fraction of a total cache word. The microprocessor integrated circuit itself has a modular cache memory array of variable size, and includes a central region having a processor unit disposed therein, a peripheral region designated as a cache memory array region surrounding the central region, and a predetermined number of cache memory sub-arrays disposed in the peripheral region such that the cache memory sub-arrays compose a modular cache memory array of variable size.

Abstract: An improved self-restore circuit and method for restoring the output line of a dynamic logic circuit. The self-restore circuit includes two transistors connected in series between the output line and the reference voltage node. The first transistor activates after an evaluation of the output line, while the second transistor only activates subsequent to the activation of the first transistor and the completion of an evaluation cycle. The self-restore circuit reduces the power consumption and safeguards against any soft error hits, wherein the second transistor protects against any soft error hits by actively pulling up the output line to the appropriate voltage.

Abstract: According to the present invention, a comparison circuit for combining a plurality of data bits is provided. One version of the invention includes a comparator which provides a signal responsive to a comparison of the voltage states of at least two of the plurality of data bits, and an amplifier which is coupled to the comparator and compares the signal provided by the comparator to a reference voltage to provide an output signal, the reference voltage being between a high and a low voltage state.