Patents by Inventor George Moussa
George Moussa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10547672Abstract: An autoscaling system for scaling resource instances in a cloud network includes an autoscaling application is stored in memory and executed by a processor. The autoscaling application is configured to provide an interface to define an autoscale policy including scale in rules and scale out rules for a plurality of different types of resource instances of a tenant. The autoscaling application is configured to receive capacity data corresponding to a first type of the plurality of different types of resource instances; calculate an estimated instance count for scaling in the first type based on the capacity data and scale in rules; calculate a projection factor based on an estimated instance count and a current instance count; generate adjusted capacity data based on current capacity data and the projection factor; compare the adjusted capacity data and the scale out rules; and selectively scale in the first type based on the comparison.Type: GrantFiled: April 27, 2017Date of Patent: January 28, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Andy Shen, George Moussa, Ashwin Kamath Govinda
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Publication number: 20180316759Abstract: An autoscaling system for scaling resource instances in a cloud network includes a processor and memory. An autoscaling application is stored in memory and executed by the processor and is configured to provide an interface to define an autoscale policy for a plurality of different types of resource instances. The autoscale policy at least one of defines minimum and maximum values for at least one of a capacity and a resource instance count for the plurality of different types of the resource instances using a common protocol and defines metric-based rules for the plurality of different types of the resource instances using the common protocol. The autoscaling application at least one of scales in or scales out the plurality of different types of the resource instances based on the autoscale policy.Type: ApplicationFiled: April 27, 2017Publication date: November 1, 2018Applicant: Microsoft Technology Licensing, LLCInventors: Andy SHEN, George MOUSSA, Ashwin KAMATH GOVINDA, Stephen Christopher SICILIANO
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Publication number: 20180316751Abstract: An autoscaling system for scaling resource instances in a cloud network includes an autoscaling application is stored in memory and executed by a processor. The autoscaling application is configured to provide an interface to define an autoscale policy including scale in rules and scale out rules for a plurality of different types of resource instances of a tenant. The autoscaling application is configured to receive capacity data corresponding to a first type of the plurality of different types of resource instances; calculate an estimated instance count for scaling in the first type based on the capacity data and scale in rules; calculate a projection factor based on an estimated instance count and a current instance count; generate adjusted capacity data based on current capacity data and the projection factor; compare the adjusted capacity data and the scale out rules; and selectively scale in the first type based on the comparison.Type: ApplicationFiled: April 27, 2017Publication date: November 1, 2018Applicant: Microsoft Technology Licensing, LLCInventors: Andy SHEN, George MOUSSA, Ashwin KAMATH GOVINDA
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Patent number: 10108340Abstract: Embodiments of the present invention receive I/O commands expressed in either vendor-specific or non-vendor-specific protocols and normalize them into a common format for execution by different memory devices. Embodiments of the present invention identify these I/O commands using parameters common to both types of protocols. In this fashion, embodiments store normalized commands in data structures for execution by memory devices in which the normalized commands represent instructions for performing an action corresponding with execution of the original I/O command. Accordingly, embodiments of the present invention save resources with respect to hardware and software maintenance costs.Type: GrantFiled: January 11, 2016Date of Patent: October 23, 2018Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Sriram Rupanagunta, Ashish Singhai, Sandeep Sharma, Srikant Sadasivam, Krishanth Skandakumaran, George Moussa, Rajendra Prasad Mishra, Kenneth Alan Okin
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Patent number: 9886196Abstract: Embodiments of the present invention are operable to efficiently schedule memory device commands, such as flash memory device commands, while taking into account the interdependencies of processing such commands. As such embodiments of the present invention order commands to make sure that data is written and read from memory devices in a coherent fashion using command groups. Commands within such command groups are scheduled concurrently or in parallel. In this fashion, embodiments of the present invention promote efficient execution of memory device commands while maintaining any required arbitrary ordering requirements.Type: GrantFiled: January 11, 2016Date of Patent: February 6, 2018Assignee: Western Digital Technologies, Inc.Inventors: Sriram Rupanagunta, Ashish Singhai, Sandeep Sharma, Srikant Sadasivam, Krishanth Skandakumaran, George Moussa, Rajendra Prasad Mishra, Kenneth Alan Okin
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Publication number: 20180008927Abstract: In general, embodiments of the present invention are related to an apparatus and method of use of such apparatus for the personal filtration of air. Particularly, embodiments of this invention relate to the filtration of air for a singular individual to inhale.Type: ApplicationFiled: July 7, 2017Publication date: January 11, 2018Inventor: George Moussa Makdissi
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Patent number: 9767867Abstract: A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.Type: GrantFiled: September 2, 2013Date of Patent: September 19, 2017Assignee: Virident Systems, Inc.Inventors: Kenneth Alan Okin, George Moussa, Kumar Ganapathy, Vijay Karamcheti, Rajesh Parekh
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Publication number: 20170115887Abstract: Embodiments of the present invention are operable to efficiently schedule memory device commands, such as flash memory device commands, while taking into account the interdependencies of processing such commands. As such embodiments of the present invention order commands to make sure that data is written and read from memory devices in a coherent fashion using command groups. Commands within such command groups are scheduled concurrently or in parallel. In this fashion, embodiments of the present invention promote efficient execution of memory device commands while maintaining any required arbitrary ordering requirements.Type: ApplicationFiled: January 11, 2016Publication date: April 27, 2017Inventors: Sriram RUPANAGUNTA, Ashish SINGHAI, Sandeep SHARMA, Srikant SADASIVAM, Krishanth SKANDAKUMARAN, George MOUSSA, Rajendra Prasad MISHRA, Kenneth Alan Okin
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Publication number: 20170115888Abstract: Embodiments of the present invention receive I/O commands, expressed in either vendor-specific or non-vendor-specific protocols and normalize them into a common format for execution by different memory devices. Embodiments of the present invention identify these I/O commands using parameters common to both types of protocols. In this fashion, embodiments store normalized commands in data structures for execution by memory devices in which the normalized, commands represent instructions for performing an action corresponding with execution of the original I/O command. Accordingly, embodiments of the present invention save resources with respect to hardware and software maintenance costs.Type: ApplicationFiled: January 11, 2016Publication date: April 27, 2017Inventors: Sriram Rupanagunta, Ashish Singhai, Sandeep Sharma, Srikant Sadasivam, Krishanth Skandakumaran, George Moussa, Rajendra Prasad Mishra, Kenneth Alan Okin
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Patent number: 8874843Abstract: A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module.Type: GrantFiled: January 25, 2013Date of Patent: October 28, 2014Assignee: Virident Systems, Inc.Inventors: Kenneth Alan Okin, George Moussa, Kumar Ganapathy, Vijay Karamcheti, Rajesh Parekh
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Patent number: 8719465Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.Type: GrantFiled: January 30, 2013Date of Patent: May 6, 2014Assignee: Intel CorporationInventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Publication number: 20140075106Abstract: A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.Type: ApplicationFiled: September 2, 2013Publication date: March 13, 2014Inventors: Kenneth A. Okin, George Moussa, Kumar Ganapathy, Vijay Karamcheti, Rajesh Parekh
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Patent number: 8598977Abstract: A method and system for monitoring and controlling driver performance in a controlled driving environment. A portable information device is provided to a driver who registers with a server computer for controlling vehicle operation in the driving environment. A record for the driver is stored in a database associated with the server computer. A vehicle is activated using the portable information device for at least an amount of time exceeding a preset threshold value. A speed level and a safety level for the vehicle are dynamically set based on the driver's performance in the driving environment. The driver's performance is monitored in the controlled driving environment and each driving violation that occurs is determined. Violation points are assigned to the driver based on each driving violation and the violation points are added to the driver record stored in the database.Type: GrantFiled: April 15, 2011Date of Patent: December 3, 2013Assignee: Tiny Towne International LLCInventors: Pierre Maalouf, Georges Moussa
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Patent number: 8463993Abstract: A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module.Type: GrantFiled: December 5, 2011Date of Patent: June 11, 2013Assignee: Virident Systems, Inc.Inventors: Kenneth Alan Okin, George Moussa, Kumar Ganapathy, Vijay Karamcheti, Rajesh Parekh
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Publication number: 20130138877Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.Type: ApplicationFiled: January 30, 2013Publication date: May 30, 2013Inventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Publication number: 20130138874Abstract: A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module.Type: ApplicationFiled: January 25, 2013Publication date: May 30, 2013Inventors: Kenneth Alan Okin, George Moussa, Kumar Ganapathy, Vijay Karamcheti, Rajesh Parekh
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Patent number: 8386665Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.Type: GrantFiled: June 28, 2011Date of Patent: February 26, 2013Assignee: Intel CorporationInventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Publication number: 20120079181Abstract: A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module.Type: ApplicationFiled: December 5, 2011Publication date: March 29, 2012Inventors: Kenneth A. Okin, George Moussa, Kumar Ganapathy, Vijay Karamcheti, Rajesh Parekh
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Publication number: 20110320672Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.Type: ApplicationFiled: June 28, 2011Publication date: December 29, 2011Inventors: Kumar Ganapathy, Ruban Kanapathippillai, Saurin Shah, George Moussa, Earle F. Philhower, III, Ruchir Shah
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Patent number: 8074022Abstract: A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.Type: GrantFiled: September 28, 2007Date of Patent: December 6, 2011Assignee: Virident Systems, Inc.Inventors: Kenneth Alan Okin, George Moussa, Kumar Ganapathy, Vijay Karamcheti, Rajesh Parekh