Abstract: A video training device and method for enabling a student athlete to closely pattern his dynamic technique after that of a recognized master. The exemplary device includes a pair of video cameras that transmit live images of the student as seen from those directions that best represent the technique. A video overlay generator receives the live images and combines them, while still in their video signal format, with a corresponding set of self-generated template images that represent, in static outline form, the dynamic technique of the master in the desired sport situation. The combined sets of images are sent to a pair of visual monitors for simultaneous, superimposed display of each set on a respective screen. User-operated controls on the video overlay generator permit the static image on each screen to be adjusted in size, moved vertically or horizontally, or switched to a new static image representing a different sport situation.

Abstract: A digital data processor includes a plurality of memory registers, a floating point adder and a floating point multiplier intercoupled by a plurality of simultaneously operable parallel buses facilitating multiple parallel operations during one clock cycle or instruction. The floating adder and multiplier each include a number of stages separated by intermediate temporary storage registers which receive the partial results of a computation for use by the next stage during the next clock period. Floating point additions, multiplications and other arithmetic and logical results are produced during each clock cycle. Memory registers comprise a data pad having a plurality of selectable stack registers and means for writing information into said data pad during one clock cycle for retrieval during the next clock cycle.

Abstract: A digital data processor includes a plurality of memory registers, a floating point adder and a floating point multiplier intercoupled by a plurality of simultaneously operable parallel buses facilitating multiple parallel operations during one clock cycle or instruction. The floating adder and multiplier each include a number of stages separated by intermediate temporary storage registers which receive the partial results of a computation for use by the next stage during the next clock period. Floating point additions, multiplications and other arithmetic and logical results are produced during each clock cycle.