Patents by Inventor George Palaskas

George Palaskas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7274760
    Abstract: Techniques are provided for the implementation of a signal processing circuit which expands the dynamic range of the signal processing circuit without interrupting the output of the circuit. The techniques can receive an input signal, process the signal through one of a plurality of signal processing circuits, and switch to processing the signal through another of the plurality of signal processing circuits without disturbing the output of the system.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: September 25, 2007
    Inventors: George Palaskas, Yannis Tsividis
  • Patent number: 7180939
    Abstract: Techniques are provided for the implementation of a signal processing circuit (100) which expands the dynamic range of the signal processing circuit (100) without interrupting the output of the circuit. The techniques can receive an input signal (104), process the signal (104) through one of a plurality of dynamically modifiable signal processing circuits, and switch (130) to processing the signal through another of the plurality of signal processing circuits without disturbing the output of the system.
    Type: Grant
    Filed: January 10, 2002
    Date of Patent: February 20, 2007
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: George Palaskas, Yannis Tsividis, Laszlo Toth
  • Patent number: 6958644
    Abstract: A signal processing system (100) comprises an input terminal (102), and a main path having a main filter input gain unit (126) coupled to said input terminal (102), a main filter (132) and an output gain unit (138). An auxiliary path includes an auxiliary filter input gain unit (106) coupled to the input terminal (102), an auxiliary filter (112) and an auxiliary filter output gain unit (118). An adder (144) is coupled to the output gain units (118, 138) for generating an output signal to an output terminal (148). The gains of the gain units are adjusted by a control unit (18) responsive to a detecting signal from a detector (160).
    Type: Grant
    Filed: January 10, 2002
    Date of Patent: October 25, 2005
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: George Palaskas, Yannis Tsividis, Laszlo Toth
  • Patent number: 6822505
    Abstract: A transconductance-setting circuit (10, 20) and method. The circuit (10, 20) includes a first transconductor (14) coupled to a reference voltage (Vref) adapted to produce a current output (Ibias). A reference current source (Iref) is coupled to the first, transconductor (14), and a feedback loop (16) is coupled to the first transconductor (14) and the reference current source (Iref). The feedback loop (16) is adapted to reduce error in the current output (2i) and set the transconductance gm of the first transconductor (14) to a value proportional to the ratio of the reference current and the reference voltage. An auxiliary transconductor (22) is coupleable to the first transconductor (14), and control circuitry (30, 40) is adapted to control the coupling of the auxiliary transconductor (22) to the first transconductor (14) based on the current output (2i).
    Type: Grant
    Filed: December 27, 1999
    Date of Patent: November 23, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: George Palaskas, Shanthi Y. Pavan
  • Publication number: 20040169551
    Abstract: A signal processing system (100) comprises an input terminal (102), and a main path having a main filter input gain unit (126) coupled to said input terminal (102), a main filter (132) and an output gain unit (138). An auxiliary path includes an auxiliary filter input gain unit (106) coupled to the input terminal (102), an auxiliary filter (112) and an auxiliary filter output gain unit (118). An adder (144) is coupled to the output gain units (118, 138) for generating an output signal to an output terminal (148). The gains of the gain units are adjusted by a control unit (18) responsive to a detecting signal from a detector (160).
    Type: Application
    Filed: April 9, 2004
    Publication date: September 2, 2004
    Inventors: George Palaskas, Yannis Tsividis, Laszlo Toth
  • Publication number: 20040091035
    Abstract: Techniques are provided for the implementation of a signal processing circuit (100) which expands the dynamic range of the signal processing circuit (100) without interrupting the output of the circuit. The techniques can receive an input signal (104), process the signal (104) through one of a plurality of dynamically modifiable signal processing circuits, and switch (130) to processing the signal through another of the plurality of signal processing circuits without disturbing the output of the system.
    Type: Application
    Filed: December 17, 2003
    Publication date: May 13, 2004
    Inventors: George Palaskas, Yannis Tsividis, Laszlo Toth
  • Publication number: 20040042572
    Abstract: Techniques are provided for the implementation of a signal processing circuit which expands the dynamic range of the signal processing circuit without interrupting the output of the circuit. The techniques can receive an input signal, process the signal through one of a plurality of signal processing circuits, and switch to processing the signal through another of the plurality of signal processing circuits without disturbing the output of the system.
    Type: Application
    Filed: June 25, 2003
    Publication date: March 4, 2004
    Inventors: George Palaskas, Yannis Tsividis
  • Patent number: 6580324
    Abstract: A system, method and apparatus are disclosed for common-mode voltage feedback. The preferred system includes a plurality of differential circuits, a corresponding plurality of common-mode voltage detectors, a corresponding plurality of buffer circuits, and a common-mode control circuit. Each differential circuit is operative to produce a first differential output voltage and a second differential output voltage. Each corresponding common-mode voltage detector is operative to provide a common-mode voltage from the first differential output voltage and the second differential output voltage. The common-mode control circuit provides a control voltage signal from the common-mode voltage and from a reference voltage. Each buffer circuit is operative to adjust the corresponding common-mode voltage using the control voltage signal to provide a common-mode feedback voltage signal to the corresponding differential circuit.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: June 17, 2003
    Assignee: Agere Systems, Inc.
    Inventors: George Palaskas, Vladimir I. Prodanov
  • Publication number: 20030048136
    Abstract: A system, method and apparatus are disclosed for common-mode voltage feedback. The preferred system includes a plurality of differential circuits, a corresponding plurality of common-mode voltage detectors, a corresponding plurality of buffer circuits, and a common-mode control circuit. Each differential circuit is operative to produce a first differential output voltage and a second differential output voltage. Each corresponding common-mode voltage detector is operative to provide a common-mode voltage from the first differential output voltage and the second differential output voltage. The common-mode control circuit provides a control voltage signal from the common-mode voltage and from a reference voltage. Each buffer circuit is operative to adjust the corresponding common-mode voltage using the control voltage signal to provide a common-mode feedback voltage signal to the corresponding differential circuit.
    Type: Application
    Filed: September 12, 2001
    Publication date: March 13, 2003
    Inventors: George Palaskas, Vladimir I. Prodanov