Patents by Inventor George R. Leal
George R. Leal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10424521Abstract: A method includes fabricating a set of die in a production run, each die comprising a set of pads at a periphery of a top metal layer, a first set of fuse elements, and a second set of fuse elements. Each fuse element of the first set of fuse elements couples a corresponding pad of the set to a corresponding bus when in a conductive state, and each fuse element of the second set couples a corresponding subset of pads of the set together when in a conductive state. The method further includes selecting a subset of the die of the production run for testing, and configuring each die of the subset for testing by placing each fuse element of the first set in a non-conductive state and placing each fuse element of the second set in a conductive state.Type: GrantFiled: May 13, 2014Date of Patent: September 24, 2019Assignee: NXP USA, INC.Inventor: George R. Leal
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Patent number: 9640469Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).Type: GrantFiled: September 10, 2015Date of Patent: May 2, 2017Assignee: NXP USA, Inc.Inventors: George R. Leal, Tim V. Pham
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Publication number: 20160005682Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).Type: ApplicationFiled: September 10, 2015Publication date: January 7, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: George R. Leal, Tim V. Pham
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Publication number: 20150332980Abstract: A method includes fabricating a set of die in a production run, each die comprising a set of pads at a periphery of a top metal layer, a first set of fuse elements, and a second set of fuse elements. Each fuse element of the first set of fuse elements couples a corresponding pad of the set to a corresponding bus when in a conductive state, and each fuse element of the second set couples a corresponding subset of pads of the set together when in a conductive state. The method further includes selecting a subset of the die of the production run for testing, and configuring each die of the subset for testing by placing each fuse element of the first set in a non-conductive state and placing each fuse element of the second set in a conductive state.Type: ApplicationFiled: May 13, 2014Publication date: November 19, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventor: George R. Leal
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Patent number: 9159643Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).Type: GrantFiled: September 14, 2012Date of Patent: October 13, 2015Assignee: Freescale Semiconductor, Inc.Inventors: George R. Leal, Tim V. Pham
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Patent number: 9142434Abstract: Methods for forming electronic assemblies are provided. A device substrate having a plurality of electronic components embedded therein is provided. The device substrate is attached to a carrier substrate using an adhesive material. A plurality of cuts are formed through the device substrate to divide the device substrate into a plurality of portions. Each of the plurality of portions includes at least one of the electronic components. A force is applied to each of the plurality of portions in a direction away from the carrier substrate to remove the plurality of portions from the carrier substrate.Type: GrantFiled: October 23, 2008Date of Patent: September 22, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Wei Gao, Craig S. Amrine, Zhiwei Gong, Scott M. Hayes, Lizabeth Ann Keser, George R. Leal, William H. Lytle
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Patent number: 9107303Abstract: An electronic panel assembly (EPA) includes one or more electronic devices with primary faces having electrical contacts, opposed rear faces and edges therebetween. The devices are mounted primary faces down in openings in a warp control sheet (WCS). Cured plastic encapsulation is formed at least between lateral edges of the devices and WCS openings. Undesirable panel warping during encapsulation is mitigated by choosing the WCS coefficient of thermal expansion (CTE) to be less than the encapsulation CTE. Thin film insulators and conductors couple electrical contacts on various devices to each other and to external terminals, thereby forming an integrated multi-device EPA.Type: GrantFiled: August 29, 2014Date of Patent: August 11, 2015Assignee: Freescale Semiconductor, Inc.Inventors: William H. Lytle, Scott M. Hayes, George R. Leal
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Patent number: 8970026Abstract: A first set of electrically conductive cladding is disposed on an inner section of one external side of a package substrate. The first set electrically conductive cladding is fabricated with a first solder compound. A second set of electrically conductive cladding is disposed on an outer section of the one external side of the substrate. The second set of electrically conductive cladding consists of a second solder compound. The outer section can be farther away from a center of the one external side of the substrate than the inner section. During a reflow process, the first and second solder compounds are configured to become completely molten when heated and the first solder compound solidifies at a higher temperature during cool down than the second solder compound.Type: GrantFiled: February 12, 2013Date of Patent: March 3, 2015Assignee: Freescale Semiconductor, Inc.Inventors: George R. Leal, Leo M. Higgins, III, Tim V. Pham
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Publication number: 20140369015Abstract: An electronic panel assembly (EPA) includes one or more electronic devices with primary faces having electrical contacts, opposed rear faces and edges therebetween. The devices are mounted primary faces down in openings in a warp control sheet (WCS). Cured plastic encapsulation is formed at least between lateral edges of the devices and WCS openings. Undesirable panel warping during encapsulation is mitigated by choosing the WCS coefficient of thermal expansion (CTE) to be less than the encapsulation CTE. Thin film insulators and conductors couple electrical contacts on various devices to each other and to external terminals, thereby forming an integrated multi-device EPA.Type: ApplicationFiled: August 29, 2014Publication date: December 18, 2014Inventors: WILLIAM H. LYTLE, Scott M. Hayes, George R. Leal
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Patent number: 8877523Abstract: A method for making a packaged integrated circuit is provided. The method includes making a first panel of encapsulated die. In some embodiments, if a threshold number of die are not positioned in proper positions in the first panel, the die are separated from the first panel. The separated die are subsequently encapsulated in other panels of encapsulated die. Conductive interconnects can be formed over the other panels. The other panels are then separated into integrated circuit packages.Type: GrantFiled: June 22, 2011Date of Patent: November 4, 2014Assignee: Freescale Semiconductor, Inc.Inventor: George R. Leal
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Patent number: 8829661Abstract: Methods and apparatus are provided for an electronic panel assembly (EPA) (82, 83), comprising: providing one or more electronic devices (30) with primary faces (31) having electrical contacts (36), opposed rear faces (33) and edges (32) therebetween. The devices (30) are mounted primary faces (31) down on a temporary support (60) in openings (44) in a warp control sheet (WCS) (40) attached to the support (60). Plastic encapsulation (50) is formed at least between lateral edges (32, 43) of the devices (30) and WCS openings (44). Undesirable panel warping (76) during encapsulation is mitigated by choosing the WCS coefficient of thermal expansion (CTE) to be less than the encapsulation CTE. After encapsulation cure, the EPA (82) containing the devices (30) and the WCS (40) is separated from the temporary support (60) and, optionally, mounted on another carrier (70) with electrical contacts (36) exposed.Type: GrantFiled: March 10, 2006Date of Patent: September 9, 2014Assignee: Freescale Semiconductor, Inc.Inventors: William H. Lytle, Scott M. Hayes, George R. Leal
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Publication number: 20140225268Abstract: A first set of electrically conductive cladding is disposed on an inner section of one external side of a package substrate. The first set electrically conductive cladding is fabricated with a first solder compound. A second set of electrically conductive cladding is disposed on an outer section of the one external side of the substrate. The second set of electrically conductive cladding consists of a second solder compound. The outer section can be farther away from a center of the one external side of the substrate than the inner section. During a reflow process, the first and second solder compounds are configured to become completely molten when heated and the first solder compound solidifies at a higher temperature during cool down than the second solder compound.Type: ApplicationFiled: February 12, 2013Publication date: August 14, 2014Inventors: GEORGE R. LEAL, Leo M. Higgins, III, Tim V. Pham
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Publication number: 20140077352Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Inventors: George R. Leal, Tim V. Pham
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Patent number: 8368172Abstract: A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state.Type: GrantFiled: July 22, 2011Date of Patent: February 5, 2013Assignee: Freescale Semiconductor, Inc.Inventors: George R. Leal, Kevin J. Hess, Trent S. Uehling
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Publication number: 20130023091Abstract: A method for forming a semiconductor structure includes forming a plurality of fuses over a semiconductor substrate; forming a plurality of interconnect layers over the semiconductor substrate and a plurality of interconnect pads at a top surface of the plurality of interconnect layers; and forming a seal ring, wherein the seal ring surrounds active circuitry formed in and on the semiconductor substrate, the plurality of interconnect pads, and the plurality of fuses, wherein each fuse of the plurality of fuses is electrically connected to a corresponding interconnect pad of the plurality of interconnect pads and the seal ring, and wherein when each fuse of the plurality of fuses is in a conductive state, the fuse electrically connects the corresponding interconnect pad to the seal ring.Type: ApplicationFiled: July 22, 2011Publication date: January 24, 2013Inventors: George R. Leal, Kevin J. Hess, Trent S. Uehling
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Publication number: 20130020674Abstract: A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state.Type: ApplicationFiled: July 22, 2011Publication date: January 24, 2013Inventors: GEORGE R. LEAL, Kevin J. Hess, Trent S. Uehling
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Patent number: 8349666Abstract: A method for forming a semiconductor structure includes forming a plurality of fuses over a semiconductor substrate; forming a plurality of interconnect layers over the semiconductor substrate and a plurality of interconnect pads at a top surface of the plurality of interconnect layers; and forming a seal ring, wherein the seal ring surrounds active circuitry formed in and on the semiconductor substrate, the plurality of interconnect pads, and the plurality of fuses, wherein each fuse of the plurality of fuses is electrically connected to a corresponding interconnect pad of the plurality of interconnect pads and the seal ring, and wherein when each fuse of the plurality of fuses is in a conductive state, the fuse electrically connects the corresponding interconnect pad to the seal ring.Type: GrantFiled: July 22, 2011Date of Patent: January 8, 2013Assignee: Freescale Semiconductor, Inc.Inventors: George R. Leal, Kevin J. Hess, Trent S. Uehling
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Publication number: 20120329212Abstract: A method for making a packaged integrated circuit is provided. The method includes making a first panel of encapsulated die. In some embodiments, if a threshold number of die are not positioned in proper positions in the first panel, the die are separated from the first panel. The separated die are subsequently encapsulated in other panels of encapsulated die. Conductive interconnects can be formed over the other panels. The other panels are then separated into integrated circuit packages.Type: ApplicationFiled: June 22, 2011Publication date: December 27, 2012Inventor: George R. Leal
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Patent number: 8216918Abstract: A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.Type: GrantFiled: July 23, 2010Date of Patent: July 10, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Zhiwei Gong, Scott M. Hayes, George R. Leal, Douglas G. Mitchell, Jason R. Wright, Jianwen Xu
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Publication number: 20120021565Abstract: A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.Type: ApplicationFiled: July 23, 2010Publication date: January 26, 2012Inventors: Zhiwei Gong, Scott M. Hayes, George R. Leal, Douglas G. Mitchell, Jason R. Wright, Jianwen Xu