Abstract: The present application relates to an infusion set (80). The infusion set (80) has a base (90) for mounting on a user, and a connector (100) which engages with the base (90) to form a flow path between the connector (100) and a cannula mountable on the base (90). The connector (100) is configured to be selectably mountable to the base (90) in at least two predetermined mounting orientations. The present application also relates to an infusion set base (90), an infusion set connector (100), an infusion set cannula, and a method of assembling an infusion set (80).

Abstract: One embodiment of the present invention sets forth a technique for increasing available storage space within compressed blocks of memory attached to data processing chips, without requiring a proportional increase in on-chip compression status bits. A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping (“swizzling”) used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data.

Abstract: The present application relates to an infusion set (80). The infusion set (80) has a base (90) for mounting on a user, and a connector (100) which engages with the base (90) to form a flow path between the connector (100) and a cannula mountable on the base (90). The connector (100) is configured to be selectably mountable to the base (90) in at least two predetermined mounting orientations. The present application also relates to an infusion set base (90), an infusion set connector (100), an infusion set cannula, and a method of assembling an infusion set (80).

Abstract: One embodiment of the present invention sets forth a technique for processing commands received by an intermediary cache from one or more clients. The technique involves receiving a first write command from an arbiter unit, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address, causing data associated with the first write command to be written into the first cache line, and marking the first cache line as dirty.

Abstract: An infusion system for delivery of therapeutic fluids from a remote source into a patient's body. The system has an infusion assembly, a rotating pivot joint member, a fluid connector assembly, and a sealing assembly retained within the infusion assembly between the housing of the infusion assembly and the rotating pivot joint member. The seal reduces leakage of fluids. The rotating joint may be pivoted to three distinct positions to allow for emplacement on the patient, delivery of the therapeutic fluid to the patient, and protected, sealed closure of the fluid channels to avoid patient fluid backflow.

Abstract: An infusion system for delivery of therapeutic fluids from a remote source into a patient's body. The system has an infusion assembly, a rotating pivot joint member, a fluid connector assembly, and a sealing assembly retained within the infusion assembly between the housing of the infusion assembly and the rotating pivot joint member. The seal reduces leakage of fluids. The rotating joint may be pivoted to three distinct positions to allow for emplacement on the patient, delivery of the therapeutic fluid to the patient, and protected, sealed closure of the fluid channels to avoid patient fluid backflow.

Abstract: A novel one-piece fluid reservoir assembly for use in conjunction with an insulin infusion pump. The single piece fluid reservoir assembly includes a barrel body, a male luer fitting integral with the barrel body, a sealing surface integral with the barrel body, the sealing surface for sealing against the pump housing when the fluid reservoir assembly is inserted into the pump housing. Further, the barrel includes, as part of the one-piece fluid reservoir assembly, threads for engagement with threads on an opening in the fluid pump so that the fluid assembly can be inserted into the fluid pump, engage the threads and rotation therewith will locate the fluid reservoir assembly within the pump. Thereafter, a piston in the pump may be incrementally advanced to act upon a plunger in the barrel assembly to force a fluid within the barrel assembly through the male luer fitting and through a conduit engaged therewith to a remote infusion set.

Abstract: A method for managing memory traffic includes causing first data to be written to a data cache memory, where a first write request comprises a partial write and writes the first data to a first portion of the data cache memory, and further includes tracking the number of partial writes in the data cache memory. The method further includes issuing a fill request for one or more partial writes in the data cache memory if the number of partial writes in the data cache memory is greater than a predetermined first threshold.

Abstract: A method for cleaning dirty data in an intermediate cache is disclosed. A dirty data notification, including a memory address and a data class, is transmitted by a level 2 (L2) cache to frame buffer logic when dirty data is stored in the L2 cache. The data classes may include evict first, evict normal and evict last. In one embodiment, data belonging to the evict first data class is raster operations data with little reuse potential. The frame buffer logic uses a notification sorter to organize dirty data notifications, where an entry in the notification sorter stores the DRAM bank page number, a first count of cache lines that have resident dirty data and a second count of cache lines that have resident evict_first dirty data associated with that DRAM bank. The frame buffer logic transmits dirty data associated with an entry when the first count reaches a threshold.

Abstract: A method for managing memory traffic includes causing first data to be written to a data cache memory, where a first write request comprises a partial write and writes the first data to a first portion of the data cache memory, and further includes tracking the number of partial writes in the data cache memory. The method further includes issuing a fill request for one or more partial writes in the data cache memory if the number of partial writes in the data cache memory is greater than a predetermined first threshold.

Abstract: An infusion system for delivery of therapeutic fluids from a remote source into a patient's body. The system has an infusion assembly, a rotating pivot joint member, a fluid connector assembly, and a sealing assembly retained within the infusion assembly between the housing of the infusion assembly and the rotating pivot joint member. The seal reduces leakage of fluids. The rotating joint may be pivoted to three distinct positions to allow for emplacement on the patient, delivery of the therapeutic fluid to the patient, and protected, sealed closure of the fluid channels to avoid patient fluid backflow.

Abstract: A system and method for buffering intermediate data in a processing pipeline architecture stores the intermediate data in a shared cache that is coupled between one or more pipeline processing units and an external memory. The shared cache provides storage that is used by multiple pipeline processing units. The storage capacity of the shared cache is dynamically allocated to the different pipeline processing units as needed, to avoid stalling the upstream units, thereby improving overall system throughput.

Abstract: One embodiment of the invention sets forth a mechanism for evicting data from a data cache based on the data class of that data. The data stored in the cache lines in the data cache is categorized based on data classes that reflect the reuse potential of that data. The data classes are stored in a tag store, where each tag within the tag store corresponds to a single cache line within the data cache. When reserving a cache line for the data associated with a command, a tag look-up unit examines the data classes in the tag store to determine which data to evict. Data that has a low reuse potential is evicted at a higher priority than data that has a high reuse potential. Advantageously, evicting data that belongs to a data class that has a lower reuse potential reduces the number of cache misses within the system.

Abstract: One embodiment of the present invention sets forth a compression status cache configured to store compression information for blocks of memory stored within an external memory. A data cache unit is configured to request, in response to a cache miss, compressed data from the external memory based on compression information stored in the compression status bit cache. The compression status for active buffers is dynamically swapped into the compression status cache as needed. Different compression formats may be specified for one or more tiles within an active buffer. One advantage of the disclosed compression status cache is that a lame amount of attached memory may be allocated as compressible memory blocks, without incurring a corresponding die area cost because a portion of the compression status stored off chip in attached memory is cached in the compression status cache.

Abstract: One embodiment of the present invention sets forth a technique for increasing available storage space within compressed blocks of memory attached to data processing chips, without requiring a proportional increase in on-chip compression status bits. A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping (“swizzling”) used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data.

Abstract: One embodiment of the present invention sets forth a technique for processing commands received by an intermediary cache from one or more clients. The technique involves receiving a first write command from an arbiter unit, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address, causing data associated with the first write command to be written into the first cache line, and marking the first cache line as dirty.

Abstract: A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping (“swizzling”) used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data.

Abstract: One embodiment of the present invention sets forth a technique for performing a memory access request to compressed data within a virtually mapped memory system comprising an arbitrary number of partitions. A virtual address is mapped to a linear physical address, specified by a page table entry (PTE). The PTE is configured to store compression attributes, which are used to locate compression status for a corresponding physical memory page within a compression status bit cache. The compression status bit cache operates in conjunction with a compression status bit backing store. If compression status is available from the compression status bit cache, then the memory access request proceeds using the compression status. If the compression status bit cache misses, then the miss triggers a fill operation from the backing store. After the fill completes, memory access proceeds using the newly filled compression status information.

Abstract: A novel one-piece fluid reservoir assembly for use in conjunction with an insulin infusion pump. The single piece fluid reservoir assembly includes a barrel body, a male luer fitting integral with the barrel body, a sealing surface integral with the barrel body, the sealing surface for sealing against the pump housing when the fluid reservoir assembly is inserted into the pump housing. Further, the barrel includes, as part of the one-piece fluid reservoir assembly, threads for engagement with threads on an opening in the fluid pump so that the fluid assembly can be inserted into the fluid pump, engage the threads and rotation therewith will locate the fluid reservoir assembly within the pump. Thereafter, a piston in the pump may be incrementally advanced to act upon a plunger in the barrel assembly to force a fluid within the barrel assembly through the male luer fitting and through a conduit engaged therewith to a remote infusion set.

Abstract: One embodiment of the present invention sets forth a compression status bit cache with deterministic latency for isochronous memory clients of compressed memory. The compression status bit cache improves overall memory system performance by providing on-chip availability of compression status bits that are used to size and interpret a memory access request to compressed memory. To avoid non-deterministic latency when an isochronous memory client accesses the compression status bit cache, two design features are employed. The first design feature involves bypassing any intermediate cache when the compression status bit cache reads a new cache line in response to a cache read miss, thereby eliminating additional, potentially non-deterministic latencies outside the scope of the compression status bit cache.