Abstract: Method, apparatus and computer program product for spur detection in a sampled waveform in a mixed analog/digital system using the magnitude of the frequency response comprising acquiring a sample waveform including a set of discrete uniformly spaced samples from a target system, wherein the sample waveform is a time domain vector; applying FFT transforming the time domain vector into the frequency domain; analyzing the frequency domain response including calculating the magnitude response; and determining whether the sample waveform has spurs including comparing the magnitude response to an average noise floor threshold including determining that the magnitude response having an average noise floor value above the average noise floor threshold has one or more spurs and determining that the magnitude response having an average noise floor value below the average noise floor threshold has no spurs, wherein a spur indicates unaligned data having a delayed bit flip.

Abstract: Method, apparatus and computer program product for spur detection in a sampled waveform in a mixed analog/digital system using the phase of the frequency response comprising acquiring a sample waveform including a set of discrete uniformly spaced samples from a target system, wherein the sample waveform is a time domain vector; applying FFT transforming the time domain vector into the frequency domain; analyzing the frequency domain response including calculating the phase response; and determining whether the sample waveform has spurs including comparing the phase response to a clean phase profile including determining that the phase response having a phase profile value outside a phase deviation tolerance has one or more spurs and determining that the phase response having a phase profile value inside the phase deviation tolerance has no spurs, wherein a spur indicates unaligned data having a delayed bit flip.

Abstract: Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different skew depending on the system in which they are used. The testing apparatus may be tuned using frequency information regarding the type of signals that will be driven on the cable when installed in the target system. In one embodiment, the testing apparatus adjusts a testing cycle refresh rate for generating a testing signal which changes the frequency content of the testing signal. Using the adjusted testing cycle refresh rate results in the driver outputting a testing signal that better reflects the actual signals that will be transmitted on the cable in the target system.

Abstract: Hardware assisted high speed serial (HSS) transceiver testing including receiving, by a link layer hardware state machine on a HSS transmitting device, an instruction to generate a test pattern, wherein the test pattern comprises a sequence of data units; loading, by the link layer hardware state machine, each unique data unit into embedded random access memory (RAM); generating, by the link layer hardware state machine, the test pattern comprising the sequence of data units using the unique data units stored in the embedded RAM, wherein at least one of the unique data units is repeated in the sequence of data units of the test pattern; and sending, by the link layer hardware state machine, the generated test pattern to an input of a HSS transceiver.

Abstract: Hardware error detection on a high-speed serial (HSS) connection including tracking, by a hardware state machine on a HSS receiver, errors in a data stream, wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data: inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample; incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample; clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and incrementing, by the hardware state machine, a sample count in a sample count register.

Abstract: The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.

Abstract: The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.

Abstract: Hardware assisted high speed serial (HSS) transceiver testing including receiving, by a link layer hardware state machine on a HSS transmitting device, an instruction to generate a test pattern, wherein the test pattern comprises a sequence of data units; loading, by the link layer hardware state machine, each unique data unit into embedded random access memory (RAM); generating, by the link layer hardware state machine, the test pattern comprising the sequence of data units using the unique data units stored in the embedded RAM, wherein at least one of the unique data units is repeated in the sequence of data units of the test pattern; and sending, by the link layer hardware state machine, the generated test pattern to an input of a HSS transceiver.

Abstract: Hardware error detection on a high-speed serial (HSS) connection including tracking, by a hardware state machine on a HSS receiver, errors in a data stream, wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data: inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample; incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample; clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and incrementing, by the hardware state machine, a sample count in a sample count register.

Abstract: The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.

Abstract: The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.

Abstract: Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different skew depending on the system in which they are used. The testing apparatus may be tuned using frequency information regarding the type of signals that will be driven on the cable when installed in the target system. In one embodiment, the testing apparatus uses the frequency information to configure a programmable clock source that can be used to shape a reference clock and control a driver to match the signals in the target system. Using the clock source to modify the reference clock results in the driver outputting a testing signal that better reflects the actual signals that will be transmitted on the cable in the target system.

Abstract: The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.

Abstract: Method and apparatus for clocked data eye measurement at synchronous interfaces is provided. A receiver may generate first vector information corresponding to data received on at least one communication channel at the receiver. The receiver may generate second information regarding when the data was latched by a clock signal, the clock signal being received on a separate communication channel at the receiver. The first vector information may be combined with the second information to generate combined information, the combined information indicating a quality of latching the data.

Abstract: An apparatus includes a memory array to generate a data eye diagram. The memory array includes a plurality of rows of memory cells. The memory cells include a first row corresponding to a first sampling circuit of a first plurality of sampling circuits. The first sampling circuit is configured to compare an input voltage signal to a first reference voltage. The memory cells also include a second row corresponding to a second sampling circuit of the first plurality of sampling circuits. The second sampling circuit is configured to compare the input voltage signal to a second reference voltage. Each memory cell of the memory array is an incremental multi-bit counter.

Abstract: An apparatus includes a memory array to generate a data eye diagram. The memory array includes a plurality of rows of memory cells. The memory cells include a first row corresponding to a first sampling circuit of a first plurality of sampling circuits. The first sampling circuit is configured to compare an input voltage signal to a first reference voltage. The memory cells also include a second row corresponding to a second sampling circuit of the first plurality of sampling circuits. The second sampling circuit is configured to compare the input voltage signal to a second reference voltage. Each memory cell of the memory array is an incremental multi-bit counter.

Abstract: Method and apparatus for clocked data eye measurement at synchronous interfaces is provided. A receiver may generate first vector information corresponding to data received on at least one communication channel at the receiver. The receiver may generate second information regarding when the data was latched by a clock signal, the clock signal being received on a separate communication channel at the receiver. The first vector information may be combined with the second information to generate combined information, the combined information indicating a quality of latching the data.

Abstract: Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different skew depending on the system in which they are used. The testing apparatus may be tuned using frequency information regarding the type of signals that will be driven on the cable when installed in the target system. In one embodiment, the testing apparatus adjusts a testing cycle refresh rate for generating a testing signal which changes the frequency content of the testing signal. Using the adjusted testing cycle refresh rate results in the driver outputting a testing signal that better reflects the actual signals that will be transmitted on the cable in the target system.

Abstract: Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different skew depending on the system in which they are used. The testing apparatus may be tuned using frequency information regarding the type of signals that will be driven on the cable when installed in the target system. In one embodiment, the testing apparatus uses the frequency information to configure a programmable clock source that can be used to shape a reference clock and control a driver to match the signals in the target system. Using the clock source to modify the reference clock results in the driver outputting a testing signal that better reflects the actual signals that will be transmitted on the cable in the target system.

Abstract: The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.