Abstract: A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor connected to a first bit line, a second non-volatile memory transistor connected to a second bit line, and a source access transistor coupled to common source line. The source access transistor includes: a first diffusion region continuous with a source region of the first non-volatile memory transistor and a second diffusion region continuous with a source region of the second non-volatile memory transistor.

Abstract: A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor connected to a first bit line, a second non-volatile memory transistor connected to a second bit line, and a source access transistor coupled to common source line. The source access transistor includes: a first diffusion region continuous with a source region of the first non-volatile memory transistor and a second diffusion region continuous with a source region of the second non-volatile memory transistor.

Abstract: A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a third source region continuous with source regions of other non-volatile memory transistors located in the same row as the EEPROM cell pair.

Abstract: A non-volatile memory (NVM) system includes a set of NVM cells, each including: a NVM transistor; an access transistor coupling the NVM transistor to a corresponding bit line; and a source select transistor coupling the NVM transistor to a common source. The NVM cells are written by a two-phase operation that includes an erase phase and a program phase. A common set of bit line voltages are applied to the bit lines during both the erase and programming phases. The access transistors are turned on and the source select transistors are turned off during the erase and programming phases. A first control voltage is applied to the control gates of the NVM transistors during the erase phase, and a second control voltage is applied to the control gates of the NVM transistors during the program phase. Under these conditions, the average required number of Fowler-Nordheim tunneling operations is reduced.

Abstract: A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a drain region that extends downward through a first well region to contact a second well region. The first, second and third semiconductor regions and the second well region have a first conductivity type, and the first well region has a second conductivity type, opposite the first conductivity type.

Abstract: A non-volatile memory (NVM) system includes a set of NVM cells, each including: a NVM transistor; an access transistor coupling the NVM transistor to a corresponding bit line; and a source select transistor coupling the NVM transistor to a common source. The NVM cells are written by a two-phase operation that includes an erase phase and a program phase. A common set of bit line voltages are applied to the bit lines during both the erase and programming phases. The access transistors are turned on and the source select transistors are turned off during the erase and programming phases. A first control voltage is applied to the control gates of the NVM transistors during the erase phase, and a second control voltage is applied to the control gates of the NVM transistors during the program phase. Under these conditions, the average required number of Fowler-Nordheim tunneling operations is reduced.

Abstract: A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a third source region continuous with source regions of other non-volatile memory transistors located in the same row as the EEPROM cell pair.

Abstract: A dual mode high voltage power supply circuit using an external high voltage connected through an internal high voltage switch which determines whether the memory blocks of a non-volatile memory circuit are programmed in a first mode from an internal high voltage charge pump or are programmed in a second mode from an external high voltage power supply connected in parallel to the internal high voltage charge pump. When the dual mode high voltage power supply circuit is operating in the first mode using only its internal change pump high voltage, it operates in a low power, low-speed mode, programming only one or two bits at a time but allowing the charge pump area on the die to be small.

Abstract: A dual mode high voltage power supply circuit using an external high voltage connected through an internal high voltage switch which determines whether the memory blocks of a non-volatile memory circuit are programmed in a first mode from an internal high voltage charge pump or are programmed in a second mode from an external high voltage power supply connected in parallel to the internal high voltage charge pump. When the dual mode high voltage power supply circuit is operating in the first mode using only its internal change pump high voltage, it operates in a low power, low-speed mode, programming only one or two bits at a time but allowing the charge pump area on the die to be small.

Abstract: A complete voice record and playback system capable of being powered by a single 1.8 VDC battery is operated in either stand-alone or CPU modes. In the stand-alone mode, two-button operation controls record, play, and memory erase functions. In CPU mode, commands may be provided through a serial interface which directly control record, playback, specialized memory management functions, and power amplifier gain settings. Through a serial interface, the system may be set up to directly write to external memory, using an analog signal generated by a microphone or other analog input device, or may instead be set up so that digital data provided by an external CPU and converted to analog using the on-chip D/A converter may be output by the speaker in real-time.

Abstract: A sector programmable EEPROM memory capable of emulating the byte programmable functionality of full-featured byte programmable EEPROMs. The EEPROM memory incorporates an on-chip write cache used as a buffer between byte level data entered by the user system and word level data written to the main memory core. The EEPROM main memory core is divided into memory pages with each memory page further divided into sub-page sectors, and each sub-page sector holding a multitude of multi-byte data words. The sub-page sectors within a memory page can be individually or collectively subjected to a program and erase cycle. The EEPROM memory incorporates an ECC unit used to recover and refresh lost data in the memory core. The EEPROM memory is also capable of interruptible load cycles.

Abstract: A sector programmable EEPROM memory capable of emulating the byte programmable functionality of full-featured byte programmable EEPROMs. The EEPROM memory incorporates an on-chip write cache used as a buffer between byte level data entered by the user system and word level data written to the main memory core. The EEPROM main memory core is divided into memory pages with each memory page further divided into sub-page sectors, and each sub-page sector holding a multitude of multi-byte data words. The sub-page sectors within a memory page can be individually or collectively subjected to a program and erase cycle. The EEPROM memory incorporates an ECC unit used to recover and refresh lost data in the memory core. The EEPROM memory is also capable of interruptible load cycles.

Abstract: Non-volatile semiconductor core memory performance is enhanced by reduced stress on core memory cells. Stress is reduced by selectable application of bias voltages to the sense line under control of the word line. The word line is connected to an inverting device in turn connected to a transistor effective for grounding the gate of a variable threshold programmable transistor in the memory cell. Power down of the word line is reflected in synchronous power-down of the sense line. Additionally, with power down, the sense amplifier for the particular core memory cell is disconnected from a master latch circuit, which in turn is connected to a slave latch circuit for applying the previous sense amplifier output to an input/output buffer, in order to secure the data sensed in core memory during read operation. The invention further permits reduced word line voltages during erase operation on the sense line and the variable threshold programmable transistor.

Abstract: Sense amplifier performance is improved in a sense amplifier circuit connected to a semiconductor memory. A current mirror circuit is connected to a data node on the side of a pass transistor adjacent to core memory. The other side of the current mirror circuit is connected to modify the current provided from a memory reference cell. This provides a lubricating current to the pass transistor to ensure that it does not shut down in the absence of current flow from a core memory cell. Sense amplifier speed is improved by a higher transconductance level in the pass transistors. Speed is improved by reducing sense node capacitance through buffer circuitry. Core performance is enhanced by interspersed reference columns within the core at distributed locations.

Abstract: An electrically programmable, electrically erasable semiconductor memory apparatus for storing information in which the equivalent of a floating gate memory device and a select transistor device are combined in a single device cell is disclosed. A single control gate both controls a select transistor and is used in programming the floating gate.

Abstract: A semiconductor memory having back-up storage devices arranged along redundant word lines to replace defective storage devices located in the primary array of the memory. The memory includes a redundant decoder for enabling the redundant word lines in response to a selected address and a redundancy disable circuit for generating a signal indicative of redundant word line use.

Abstract: A sense amplifier (124) for use in determining the binary state of a selected storage device (4) in a semiconductor memory array (2) is disclosed. The sense amplifier (124) comprises a sensing section (150), a reference signal generator (148), and an inverting amplifier section (152). A relatively small current transistor (164) connected between a source of operating potential (158) and a voltage node (162) in the sensing section (150) supplies read currents to the selected storage device (4) via an enabled bit line (8) in the array (2). A second transistor (168) of relatively large size connected to the voltage node (162) in parallel with the current transistor (164) operates to rapidly raise the potential on the bit line (8) when the bit line (8) is first enabled. A third transistor (166) also of relatively large size connected between the voltage node (162) and the bit line (8) serves as a transfer gate for read currents. The reference signal generator (148) feeds a reference potential V.sub.

Abstract: Circuitry for isolating and rendering inoperative faulty storage devices in a semiconductor memory array is disclosed. A determination is made as to whether the x-addresses of the faulty storage devices contain an address bit having a common value for all of the faulty storage devices. If such an address bit exists, the address buffer associated with the common address bit is programmed to lock in a permanent set of address indicator outputs. All x-address locations accessed by address signals containing the common address bit are thereafter disabled. The memory array continues to function at half its former storage capacity, using the storage devices associated with the remaining address locations.