Abstract: Briefly stated, the disclosed technology is generally directed to integrated circuit (IC) technology for an IoT processor. In one example, multiple components may be tightly or otherwise integrated onto a single die, e.g., a single monolithic integrated circuit. In one basic example, the components may include a security processing unit and a radio. The components may also include one or more microprocessors (e.g., a processor capable of executing a high-level operating system), microcontrollers, secure memories, encryption components, peripheral interfaces, and/or the like. The security processing unit and/or the configuration of the components may enable, facilitate, or otherwise provide for security features such as tamper resistance, data security, and/or the like.

Abstract: A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1x double data rate memory speed, and means for receiving data and strobe signals via said pads at Mx double data rate memory speed (M2).

Abstract: A memory controller is provided with a memory to store indications of data/strobe ratios that are required to access memory devices that are coupled to the memory controller. The memory controller is also provided with a memory interface through which the memory controller initiates data transmissions with the memory devices. For a data transmission initiated with a particular one of the memory devices, the ratio of data signals to strobe signals sent/received through the interface is dynamically determined in response to a corresponding indication of a data/strobe ratio stored in the memory.

Abstract: A memory controller is provided with a memory to store indications of data/strobe ratios that are required to access memory devices that are coupled to the memory controller. The memory controller is also provided with a memory interface through which the memory controller initiates data transmissions with the memory devices. For a data transmission initiated with a particular one of the memory devices, the ratio of data signals to strobe signals sent/received through the interface is dynamically determined in response to a corresponding indication of a data/strobe ratio stored in the memory.

Abstract: A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1x double data rate memory speed, and means for receiving data and strobe signals via said pads at Mx double data rate memory speed (M2).

Abstract: A memory controller that reads and writes memory modules populated with non-homogeneous data width RAM devices, wherein the RAM devices are of a type which send and receive data with a source synchronous strobe. The memory controller maintains a memory map and stores therein indications of data/strobe ratios which are required to read and write memory modules coupled to the memory controller. The indications of data/strobe ratios are addressed during read and write cycles of the memory controller. Addressed indications are used during write cycles to ensure that strobes are generated at a correct number of strobe pads. Addressed indications are used during read cycles to ensure that received data signals are associated with their correct and corresponding strobe signals.

Abstract: A memory controller that reads and writes memory modules populated with non-homogeneous data width RAM devices, wherein the RAM devices are of a type which send and receive data with a source synchronous strobe. The memory controller maintains a memory map and stores therein indications of data/strobe ratios which are required to read and write memory modules coupled to the memory controller. The indications of data/strobe ratios are addressed during read and write cycles of the memory controller. Addressed indications are used during write cycles to ensure that strobes are generated at a correct number of strobe pads. Addressed indications are used during read cycles to ensure that received data signals are associated with their correct and corresponding strobe signals.