Abstract: A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.

Abstract: A method and an apparatus for restoring logic states using programming code are disclosed. In one embodiment, the process of a data processing system identifies a first logic value stored in a first register and branches to a first location within the programming code based upon the first logic value. The execution of the programming code occurs in a processor firmware layer. The first register can be used as a scratch register for the subsequent instruction.

Abstract: A novel processor architecture and algorithms are provided which improve non-volatile memory updates and increases processor performance in successive generations of processors. A new processor architecture is supported by a software model consisting of two new firmware layers and the legacy 32 bit basic input output system (BIOS) firmware. The new firmware layers consist of a Processor Abstraction Layer (PAL) and a System Abstraction Layer (SAL). The PAL and SAL have procedure calls which allow updates of the firmware components in the non-volatile memory of a system, e.g. non-volatile ROM. The present invention includes invoking a system abstraction layer update procedure to implement a new input binary into the non-volatile memory. An algorithm for the non-volatile memory includes selecting a lead processor to perform an update and using the system abstraction layer update procedure. The system abstraction layer update procedure is used to call an appropriate authentication routine.

Abstract: A method and an apparatus for validating a processor firmware (“PF”) are disclosed. In one embodiment, at least one version of Processor Firmware (“PF”) is identified. After identification, the PF is compared with a version of PF that is required by a processor, to determine whether the PF is compatible with the processor. If the version of PF is incompatible with the version of PF required by the processor, the current execution is suspended and a new version of PF is obtained. When the new version of PF is received, the system is initialized.

Abstract: A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.

Abstract: A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.

Abstract: An electronic system and corresponding method for verifying the integrity of code that is stored off-chip. The electronic system comprises a memory element to store Processor Abstraction Layer (PAL) code and a processor coupled to the memory element. The processor verifies the integrity of the PAL code prior to execution of the PAL code.

Abstract: Some embodiments of the invention include a computer system comprising a bus, a processor and a computer readable medium external to the processor. The computer readable medium is coupled to the processor by the bus and stores instructions to implement microcode functions. Some other embodiments of the invention include a method of using firmware as microcode. The method comprises storing programmed code in firmware and executing the programmed code. The method further comprises updating one or more registers associated with a logic unit on the processor in response to the execution of the programmed code and controlling one or more functions of the logic unit on the processor based on a value stored in the register.

Abstract: An electronic system and corresponding method for authenticating firmware stored in a memory element external to a processor. In one embodiment, an electronic system comprises a processor and a memory element. The memory element is used to contain firmware and a digital signature of the firmware signed by a signatory. Coupled to the memory element, the processor authenticates the firmware during a predetermined condition, which occurs prior to execution of the firmware, through use of a pre-stored public key of the signatory and a pre-stored digital signature function.

Abstract: A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.

Abstract: A system and method is provided for processing interrupt requests. The method is accomplished by detecting when an interrupt request is being stored in a storage location, examining the storage location storing the interrupt request, prioritizing the interrupt request when more than one interrupt request is stored in the storage location to determine an interrupt request processing order, clearing the interrupt request in the storage location that is to be processed, and processing the interrupt request. The system comprises a first storage location for storing an interrupt request, a second storage location for storing an interrupt handler program with encoded statements for examining the first storage location, prioritizing the interrupt request that is to be processed if more than one interrupt request is stored in said first storage location, clearing the interrupt request that is to be processed, and processing the interrupt request.

Abstract: An apparatus and method for dynamically adjusting the power/performance characteristics of a memory subsystem. Since the memory subsystem access requirements are heavily dependent on the application being executed, static methods of enabling or disabling the individual memory system components (as are used in prior art) are less than optimal from a power consumption perspective. By dynamically tracking the behavior of the memory subsystem, the invention predicts the probability that the next event will have certain characteristics, such as whether it will result in a memory cycle that requires the attention of a cache memory, whether that memory cycle will result in a cache memory hit, and whether a DRAM page hit in main memory will occur if the requested data is not in one of the levels of cache memory. Based on these probabilities, the invention dynamically enables or disables components of the subsystem.

Abstract: A microprocessor includes the capability to service at least one debug exception and an I/O trap generated during execution of a single instruction. After executing each instruction, the microprocessor determines whether a debug exception and an I/O trap occurred. If at least one debug exception and an I/O trap exist, then the microprocessor determines an active status for the debug exception. The microprocessor stores the contents of internal registers, constituting a state of the microprocessor, to memory, and latches a breakpoint status for the debug exception in a public debug status register. The breakpoint status is preserved by copying the breakpoint status to a private debug status register. The microprocessor services the I/O trap by executing a SMM handler, an upon returning from the SMM handler, the state of the microprocessor is restored. If the I/O trap serviced requires instruction restart, then the state of the microprocessor is adjusted to re-execute the instruction.