Abstract: Described herein are method and apparatus for scheduling access requests for a multi-bank low-latency random read memory (LLRRM) device within a storage system. The LLRRM device comprising a plurality of memory banks, each bank being simultaneously and independently accessible. A queuing layer residing in storage system may allocate a plurality of request-queuing data structures (“queues”), each queue being assigned to a memory bank. The queuing layer may receive access requests for memory banks in the LLRRM device and store each received access request in the queue assigned to the requested memory bank. The queuing layer may then send, to the LLRRM device for processing, an access request from each request-queuing data structure in successive order. As such, requests sent to the LLRRM device will comprise requests that will be applied to each memory bank in successive order as well, thereby reducing access latencies of the LLRRM device.

Abstract: Described herein are method and apparatus for scheduling access requests for a multi-bank low-latency random read memory (LLRRM) device within a storage system. The LLRRM device comprising a plurality of memory banks, each bank being simultaneously and independently accessible. A queuing layer residing in storage system may allocate a plurality of request-queuing data structures (“queues”), each queue being assigned to a memory bank. The queuing layer may receive access requests for memory banks in the LLRRM device and store each received access request in the queue assigned to the requested memory bank. The queuing layer may then send, to the LLRRM device for processing, an access request from each request-queuing data structure in successive order. As such, requests sent to the LLRRM device will comprise requests that will be applied to each memory bank in successive order as well, thereby reducing access latencies of the LLRRM device.

Abstract: Method and apparatus for scheduling access requests for a multi-bank low-latency random read memory (LLRRM) device within a storage system. The LLRRM device comprising a plurality of memory banks, each bank being simultaneously and independently accessible. A queuing layer residing in storage system may allocate a plurality of request-queuing data structures (“queues”), each queue being assigned to a memory bank. The queuing layer may receive access requests for memory banks in the LLRRM device and store each received access request in the queue assigned to the requested memory bank. The queuing layer may then send, to the LLRRM device for processing, an access request from each request-queuing data structure in successive order. As such, requests sent to the LLRRM device will comprise requests that will be applied to each memory bank in successive order as well, thereby reducing access latencies of the LLRRM device.

Abstract: Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.

Abstract: A method of managing power states of memory modules while performing memory access operations is disclosed. Memory modules are in a power saving state until an access operation involving the module is to be performed. The module is placed in an operational mode, then the access operation is performed, then the module is returned to the power saving state. Apparatus and systems using the method are also disclosed and claimed.

Abstract: Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.

Abstract: Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.

Abstract: A system and method for protecting memory during system initialization is provided. A complex programmable logic device (CPLD) is operatively interconnected with a multiplexer to enable control of a memory to be switched between a memory controller and the CPLD in response to error conditions. If an error condition is identified, the CPLD assumes control of the memory and activates a battery subsystem to provide memory refreshes until system re-initialization. Upon system bring-up, interactions between the BIOS and CPLD assure that protected memory is fully recovered by the system. The contents of memory will remain protected from any further faults that may occur during the bring-up sequence.

Abstract: The battery apparatus introduced here provides a tool for reliably measuring the run time to empty of a battery used in a network storage server for protection of data during a failure mode. The battery run time to empty can be determined by a management controller based on battery information generated by a controller and received at the management controller. The information received at the management controller includes run time to empty, voltage, current and current battery capacity.

Abstract: A system and method protects the contents of memory during error conditions. An illustrative storage system includes a complex programmable logic device (CPLD) that interfaces with a memory controller and a basic input output system (BIOS) for ensuring that the system memory is maintained in a self refresh state in the event of an error condition. The memory controller is configured to, in response to receiving a signal from the CPLD, cause the memory to enter the self refresh state where it is maintained by a battery subsystem (or alternate power sources). Accordingly, data contained within the memory may be replayed to persistent storage upon correction of the error condition via, for example, a system re-initialization.

Abstract: A method of managing power states of memory modules while performing memory access operations is disclosed. Memory modules are in a power saving state until an access operation involving the module is to be performed. The module is placed in an operational mode, then the access operation is performed, then the module is returned to the power saving state. Apparatus and systems using the method are also disclosed and claimed.

Abstract: The battery apparatus introduced here provides a tool for reliably measuring the run time to empty of a battery used in a network storage server for protection of data during a failure mode. The battery run time to empty can be determined by a management controller based on battery information generated by a controller and received at the management controller. The information received at the management controller includes run time to empty, voltage, current and current battery capacity.

Abstract: Embodiments of the invention include a memory device, such as a removable expanded memory card, having a host bus interface that allows a host to access a memory of the device. The memory device also includes memory scrubbing circuitry to read data stored at addresses in the memory and to identify single-bit errors and multiple-bit errors in the data read from the memory.

Abstract: A file server for serving data of a client from a network. The server includes disk means for storing the data. The server includes means for receiving the data from the network and sending an acknowledgment that the data has been stored to the client through the network but before the data has been stored in the disk means, the receiving means in communication with the disk means. The server includes a memory for storing the data until the data is stored in the disk means, the receiving means is in communication with the memory. The server includes a first power source for provide electricity to the disk means, the memory and the receiving means, the first power source in electrical communication with the disk means, the memory and the receiving means. The server includes a second power source that provides electricity to the memory when the first power source fails, the second power source in communication with the memory. A method for serving data of a client from a network.

Abstract: A method of managing power states of memory modules while performing memory access operations is discussed. Memory modules are in a power saving state until an access operation involving the module is to be performed. The module is placed in an operational mode, then the access operation is performed, then the module is returned to the power saving state.

Abstract: A file server for serving data of a client from a network. The server includes disk means for storing the data. The server includes means for receiving the data from the network and sending an acknowledgment that the data has been stored to the client through the network but before the data has been stored in the disk means, the receiving means in communication with the disk means. The server includes a memory for storing the data until the data is stored in the disk means, the receiving means is in communication with the memory. The server includes a first power source for provide electricity to the disk means, the memory and the receiving means, the first power source in electrical communication with the disk means, the memory and the receiving means. The server includes a second power source that provides electricity to the memory when the first power source fails, the second power source in communication with the memory. A method for serving data of a client from a network.

Abstract: A system for storing data. The system includes a host for processing the data. The system includes a buffer mechanism for storing data and producing interrupt signals to the host for informing the host there is data in the buffer mechanism for the host to process. The buffer mechanism adapting the production of interrupts based on the speed the host can process data. The host is in contact with the buffer mechanism. A method for serving data. The method includes the steps of storing data in a buffer mechanism. Then there is the step of sending an initial interrupt signal to a host from the buffer mechanism informing the host there is data in the buffer mechanism for the host to process. Next there is the step of transferring data in the buffer mechanism to the host. Then there is the step of processing data from the buffer mechanism with the host. Next there is the step of adapting when a subsequent interrupt signal is sent to the host based on the speed the host can process data.

Abstract: An apparatus for reflecting an f-RM cell as a b-RM cell. The apparatus includes an RM cell processor which is adapted to receive the f-RM cell from an ATM network and modifies ABR information of the f-RM cell to reflect congestion regarding cells on the ATM network. The apparatus includes a transmit scheduler connected to the RM cell processor which forms the b-RM cell from the modified ABR information of the f-RM cell and sends the b-RM cell to the ATM network. The transmit scheduler is decoupled from the RM cell processor. An ATM telecommunications system. A method for reflecting an f-RM cell as a b-RM cell.

Abstract: An ATM communications system. The system includes an ATM network on which ATM cells of ATM packets travel. The system includes a host which produces ATM packets having cells which include at least a payload. The system includes an interface connected to the host which sends ATM cells from the host onto the ATM network. The interface produces read requests to the host for obtaining cells from the host. The interface transfers a partial packet having a plurality of cells from the host to the interface with each read request. The interface has a bus which connects to the host on which communication between the host and the interface occurs. The interface has a transfer mechanism which is connected to the ATM network to send cells to the ATM network. An interface for connection to a host which sends ATM cells from the host to an ATM network. A method for sending ATM cells over an ATM network.

Abstract: A method and apparatus for configuring a single point arbitration scheme for a commonly accessed communication bus using bus master devices with arbitration control circuitry included therein. Bus master devices including arbitration control circuitry may be connected to an arbitration control bus over which signals for arbitrating control to the commonly accessed communications bus are provided. During a configuration mode of operation, the same connections to the arbitration control bus provide signals which are decoded at each bus master device to provide a configuration status which indicates whether other bus master devices requiring arbitration are connected to the arbitration control bus and whether the arbitration control circuitry included on the particular device will be enabled to perform the arbitration.