Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series.

Abstract: Embodiments of the present disclosure relate to a connector to connect a printed circuit board (PCB) with a memory device, where the connector includes a housing couplable with the PCB; a first signal pin coupled with the housing, where the first signal pin includes a first portion that includes a first curve, and a second portion that extends from the first portion and includes a second curve; and a second signal pin coupled with the housing, where the second signal pin includes a third portion that includes a third curve, and a fourth portion that extends from the third portion and includes a fourth curve, where the first curve is curved in a first opposite direction relative to the third curve, and where the second curve is curved in a second opposite direction relative to the fourth curve.

Abstract: An apparatus is described. The apparatus includes a dual-in line memory module (DIMM) socket having a first electrical circuit component embedded in a latch of the DIMM socket. The first electrical circuit component has a first exposed electrical contact that is to contact or not contact a second exposed electrical contact of a second electrical circuit component that is embedded in a housing of the socket depending on whether a corner of a DIMM is or is not properly inserted into the DIMM socket.

Abstract: Embodiments are directed towards apparatuses, methods, and systems for a memory module, e.g., a dual in-line memory module (DIMM) including a first lengthwise edge along the DIMM and a second lengthwise edge, opposite the first lengthwise edge, to couple the DIMM with a printed circuit board (PCB). In embodiments, the DIMM includes one or more notches along the first lengthwise edge, to removeably couple with one or more flexible supports located at least partially along a length or width of a chassis and to engage the notches to assist in retention of the DIMM in the chassis to reduce a shock and/or vibration associated with a load of a plurality of DIMMs on the PCB. In some embodiments, the one or more flexible supports are coupled to a support structure, such as a pole mounted or otherwise coupled to a panel of the chassis. Additional embodiments may be described and claimed.

Abstract: A DIMM is described. The DIMM includes circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence.

Abstract: An embodiment of a latch apparatus for a circuit board comprises a first latch body with a retention mechanism for the circuit board, a second latch body with a coupling mechanism for a connector, and a spring mechanism mechanically coupled between the first latch body and the second latch body. Other embodiments are disclosed and claimed.

Abstract: A connector includes mounting tabs that are extended relative to traditional mounting tabs. On a back side of the printed circuit board (PCB), the mounting tabs connect to a back plate. The mounting tabs extend through the PCB and connect with the back plate, which provides improved structural integrity. Depending on the connector, the use of the mounting tabs can use existing mounting holes for the connector and remove the need for additional mounting holes.

Abstract: Examples include techniques to mirror a command/address or interpret command/address logic at a memory device. A memory device located on a dual in-line memory module (DIMM) may include circuitry having logic capable of receiving a command/address signal and mirror a command/address or interpret command/address logic indicated in the command/address signal based on one or more strap pins for the memory device.

Abstract: An embodiment of a connector housing for a circuit board may include a connector body to receive the circuit board, and a relaxation mechanism mechanically coupled to the connector body to relax stress on the connector housing and maintain the circuit board received in the connector body under a load which exceeds a load threshold. Other embodiments are disclosed and claimed.

Abstract: A memory subsystem includes a command address bus capable to be operated at double data rate. A memory circuit includes N command signal lines that operate at a data rate of 2R to receive command information from a memory controller. The memory circuit includes 2N command signal lines that operate at a data rate of R to transfer the commands to one or more memory devices. While ratios of 1:2 are specified, similar techniques can be used to send command signals at higher data rates over fewer signal lines from a host to a logic circuit, which then transfers the command signals at lower data rates over more signal lines.

Abstract: Embodiments are generally directed to high capacity energy backed memory with off device storage. A memory device includes a circuit board; multiple memory chips that are installed on the circuit board; a controller to provide for backing up contents of the memory chips when a power loss condition is detected; a connection to a backup energy source; and a connection to a backup data storage that is separate from the memory device.

Abstract: Anchoring power pins are described herein. In one embodiment, a system includes a circuit board including a through hole, and a connector for coupling a module with the circuit board. The connector includes housing including a module-facing side to receive the module and a circuit board-facing side to couple with the circuit board. The connector includes a conductive power pin to both physically anchor the connector to the circuit board and electrically couple the module with the circuit board, the conductive power pin including a tip protruding from the circuit board-facing side of the connector to extend into a matching through hole in the circuit board.

Abstract: A method and apparatus to detect, initialize and isolate a non-operating memory module in a system without physically removing the memory module from the system is provided. The memory module includes a power management integrated circuit to provide power to a memory integrated circuit on the memory module. During initialization of the memory module, if an error log stored in a non-volatile memory in the memory module indicates a fatal error condition from a prior power cycle, the memory module is electrically isolated.

Abstract: In an example, there is disclosed a memory controller, including: a data buffer to drive a determinate value to a data bus to communicatively couple to a memory; and a register clock driver to: receive a memory initialization command from a processor; and incrementally step through a plurality of initialization addresses, sequentially driving each initialization address to an address bus to communicatively couple to the memory. There is also disclosed a computing device comprising the memory controller, and a method of initializing memory comprising incrementally stepping through a plurality of initialization addresses and sequentially writing a determinate value to each address.

Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

Abstract: A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

Abstract: In one embodiment, an apparatus includes: a peer-to-peer (P2P) control circuit to issue a P2P communication request to a bus master of a multi-drop interconnect to request authorization to send a P2P transaction to at least one slave device coupled to the multi-drop interconnect; a transmitter to transmit the P2P transaction to the at least one slave device when the bus master grants the authorization for the P2P transaction; and another transmitter to output the clock signal to the multi-drop interconnect during the P2P transaction. Other embodiments are described and claimed.

Abstract: A codeset is described in a Public Codeset Communication Format (PCCF) as a format block including a plurality of fields having readily decipherable values, such as ASCII character values. One field is a mark/space information field that includes a sequence of mark time indicators and space time indicators for an operational signal of the codeset. A second field is a signal characteristic information field for the operational signal. Signal characteristic information may include carrier on/off information, repeat frame information, toggle control information, and last frame information. The PCCF is a codeset interchange format of general applicability.

Abstract: Embodiments include devices, systems, and methods relating to removing heat from a memory module in a connector. One embodiment relates to a memory module connector comprising a first arm, a second arm, and a body portion positioned between the first arm and the second arm, the body portion configured to accept a memory module therein. The memory module connector includes a structure coupled to the first arm and configured to be electrically coupled to a printed circuit board. The memory module connector also includes a heat spreader coupled to the first arm, the heat spreader configured to be brought into thermal contact with a memory module component. Other embodiments are described and claimed.