Patents by Inventor George W. Alexander
George W. Alexander has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6888365Abstract: A semiconductor wafer testing system tests one or more die clusters on a semiconductor wafer, using a test circuit to test multiple sections or areas of each die in parallel. The semiconductor wafer testing system has a buffer connected to the die cluster via the test circuit. The buffer writes test data onto a section of each die in the die cluster. The buffer reads test data from the section of each die in the die cluster.Type: GrantFiled: September 12, 2002Date of Patent: May 3, 2005Assignee: Infineon Technologies North America CorporationInventors: Daivid Suitwai Ma, James J. Dietz, George W. Alexander
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Patent number: 6845048Abstract: A system and method for monitoring internal voltage sources in an integrated circuit, such as a DRAM integrated circuit, includes an internal analog multiplexing circuit, an internal analog-to-digital converter, and an interface circuit. Through the analog multiplexing circuit, the analog-to-digital converter sequentially connects to each voltage source and converts the measured voltage level of the source to a binary word. The interface circuit presents the binary word, e.g., serially, to test equipment off the integrated circuit.Type: GrantFiled: September 25, 2002Date of Patent: January 18, 2005Assignee: Infineon Technologies AGInventors: George W. Alexander, Jennifer F. Huckaby, Steven M. Baker, David S. Ma
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Patent number: 6777990Abstract: A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a first delayed clock signal. The forward delay circuit adjustably shifts in time the first delayed clock signal relative to the reference clock signal. A fixed delay circuit receives the first delayed clock signal and issues a second delayed clock signal. A feedback delay circuit receives a selected one of the first delayed and the second delayed clock signals, and issues a feedback clock signal. The feedback clock signal is shifted in time relative to the selected one of the first delayed and the second delayed clock signals.Type: GrantFiled: March 19, 2002Date of Patent: August 17, 2004Assignee: Infineon Technologies AGInventors: Torsten Partsch, George W. Alexander
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Patent number: 6765419Abstract: A delay lock loop circuit for aligning in time a reference clock signal with an internal feedback clock signal includes a forward delay circuit that receives the reference clock signal. The forward delay circuit includes a forward delay line having a plurality of electrically interconnected delay blocks. Each of the delay blocks includes a predetermined number of electrically interconnected delay units. Disabling means deactivate the one or more delay blocks when the delay blocks are not needed in order to time align the reference clock signal and the internal feedback clock signal.Type: GrantFiled: March 11, 2002Date of Patent: July 20, 2004Assignee: Infineon Technologies AGInventor: George W. Alexander
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Publication number: 20040057289Abstract: A system and method for monitoring internal voltage sources in an integrated circuit, such as a DRAM integrated circuit, includes an internal analog multiplexing circuit, an internal analog-to-digital converter, and an interface circuit. Through the analog multiplexing circuit, the analog-to-digital converter sequentially connects to each voltage source and converts the measured voltage level of the source to a binary word. The interface circuit presents the binary word, e.g., serially, to test equipment off the integrated circuit.Type: ApplicationFiled: September 25, 2002Publication date: March 25, 2004Applicant: Infineon Technologies North America Corp.Inventors: George W. Alexander, Jennifer F. Huckaby, Steven M. Baker, David S. Ma
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Publication number: 20040051550Abstract: A semiconductor die isolation system electrically disconnects the semiconductor die from a routing mechanism when an isolation block is activated. The semiconductor die is tested through a routing mechanism connection with a testing device on a semiconductor wafer. The isolation block is activated when the testing is completed.Type: ApplicationFiled: September 12, 2002Publication date: March 18, 2004Inventors: David Suitwai Ma, George W. Alexander, James J. Dietz
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Publication number: 20040051547Abstract: A semiconductor wafer testing system tests one or more die clusters on a semiconductor wafer, using a test circuit to test multiple sections or areas of each die in parallel. The semiconductor wafer testing system has a buffer connected to the die cluster via the test circuit. The buffer writes test data onto a section of each die in the die cluster. The buffer reads test data from the section of each die in the die cluster.Type: ApplicationFiled: September 12, 2002Publication date: March 18, 2004Inventors: Daivid Suitwai Ma, James J. Dietz, George W. Alexander
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Patent number: 6693473Abstract: A delay lock loop circuit includes a forward delay circuit having a plurality of delay elements. Each delay element has a delay time of one unit delay time. The forward delay circuit and each of the delay elements are powered by a supply voltage. The supply voltage is set to thereby set the duration of a unit delay time. Moreover, a feedback delay circuit is provided in order to cause a feedback delay time being substantially equal to a propagation delay of the IC. As the operating conditions of IC change, and the propagation delay thereof increases or decreases, the feedback delay time changes accordingly, and thus the delay caused by forward delay circuit tracks the change in the propagation delay of the IC.Type: GrantFiled: March 19, 2002Date of Patent: February 17, 2004Assignee: Infineon Technologies AGInventors: George W. Alexander, Jinhwan Lee
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Patent number: 6653875Abstract: A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a delayed clock signal. The forward delay circuit adjustably shifts in time the delayed clock signal relative to the reference clock signal. An inverter receives the delayed clock signal and issues an inverted delayed clock signal. A feedback delay circuit receives a selected one of the delayed and the inverted delayed clock signals, and issues a feedback clock signal that is shifted in time relative to the selected one of the delayed and the inverted delayed clock signals. The feedback clock signal is compared to the reference clock signal. The time shift of the delayed clock signal is adjusted to thereby time-align the reference clock signal and the feedback clock signal.Type: GrantFiled: March 11, 2002Date of Patent: November 25, 2003Assignee: Infineon Technologies AGInventors: Torsten Partsch, George W. Alexander
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Publication number: 20030179026Abstract: A delay lock loop circuit includes a variable voltage regulator and a forward delay circuit. The variable voltage regulator receives an external supply voltage and issues a variable supply voltage. The forward delay circuit is powered by the variable supply voltage.Type: ApplicationFiled: March 19, 2002Publication date: September 25, 2003Applicant: Infineon Technologies North America Corp.Inventors: George W. Alexander, Jinhwan Lee
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Publication number: 20030179025Abstract: A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a first delayed clock signal. The forward delay circuit adjustably shifts in time the first delayed clock signal relative to the reference clock signal. A fixed delay circuit receives the first delayed clock signal and issues a second delayed clock signal. A feedback delay circuit receives a selected one of the first delayed and the second delayed clock signals, and issues a feedback clock signal. The feedback clock signal is shifted in time relative to the selected one of the first delayed and the second delayed clock signals.Type: ApplicationFiled: March 19, 2002Publication date: September 25, 2003Applicant: Infineon Technologies North America Corp.Inventors: Torsten Partsch, George W. Alexander
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Publication number: 20030169085Abstract: A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a delayed clock signal. The forward delay circuit adjustably shifts in time the delayed clock signal relative to the reference clock signal. An inverter receives the delayed clock signal and issues an inverted delayed clock signal. A feedback delay circuit receives a selected one of the delayed and the inverted delayed clock signals, and issues a feedback clock signal that is shifted in time relative to the selected one of the delayed and the inverted delayed clock signals. The feedback clock signal is compared to the reference clock signal. The time shift of the delayed clock signal is adjusted to thereby time-align the reference clock signal and the feedback clock signal.Type: ApplicationFiled: March 11, 2002Publication date: September 11, 2003Applicant: Infineon Technologies North America Corp.Inventors: Torsten Partsch, George W. Alexander
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Publication number: 20030169083Abstract: A delay lock loop circuit for aligning in time a reference clock signal with an internal feedback clock signal includes a forward delay circuit that receives the reference clock signal. The forward delay circuit includes a forward delay line having a plurality of electrically interconnected delay blocks. Each of the delay blocks includes a predetermined number of electrically interconnected delay units. Disabling means deactivate the one or more delay blocks when the delay blocks are not needed in order to time align the reference clock signal and the internal feedback clock signal.Type: ApplicationFiled: March 11, 2002Publication date: September 11, 2003Applicant: Infineon Technologies North America Corp.Inventor: George W. Alexander
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Patent number: 6516006Abstract: A self-adjusting path is created by utilizing a phase detector and modifying a clock path and a data path to enable the passing of data in either phase of the clock. The new input path is controlled by the output of the phase detector. Each time a command is issued, the phase of the clock is detected and latched. The phase of the clock at the time the command issues is thus captured and can propagate through the pipeline along with the data. Accordingly, each stage along the data path can be synchronized to a different phase of the clock to reduce data corruption.Type: GrantFiled: February 16, 1999Date of Patent: February 4, 2003Assignee: Mitsubishi Electric and Electronics U.S.A., Inc.Inventors: Robert M. Walker, Stephen M. Camacho, George W. Alexander